IT1256217B - Circuito di commutazione di alta tensione in particolare per dispositivi di memoria a semiconduttori. - Google Patents

Circuito di commutazione di alta tensione in particolare per dispositivi di memoria a semiconduttori.

Info

Publication number
IT1256217B
IT1256217B ITMI922927A ITMI922927A IT1256217B IT 1256217 B IT1256217 B IT 1256217B IT MI922927 A ITMI922927 A IT MI922927A IT MI922927 A ITMI922927 A IT MI922927A IT 1256217 B IT1256217 B IT 1256217B
Authority
IT
Italy
Prior art keywords
high voltage
circuit
switching circuit
voltage
voltage switching
Prior art date
Application number
ITMI922927A
Other languages
English (en)
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of ITMI922927A0 publication Critical patent/ITMI922927A0/it
Publication of ITMI922927A1 publication Critical patent/ITMI922927A1/it
Application granted granted Critical
Publication of IT1256217B publication Critical patent/IT1256217B/it

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0883—Combination of depletion and enhancement field effect transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/12—Programming voltage switching circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/143—Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels ; Switching between alternative supplies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/06—Modifications for ensuring a fully conducting state
    • H03K17/063—Modifications for ensuring a fully conducting state in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/10—Modifications for increasing the maximum permissible switched voltage
    • H03K17/102—Modifications for increasing the maximum permissible switched voltage in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/693—Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors

Landscapes

  • Power Engineering (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Electronic Switches (AREA)
  • Read Only Memory (AREA)
  • Logic Circuits (AREA)
  • Non-Volatile Memory (AREA)
  • Dc-Dc Converters (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

Un circuito di commutazione di alta tensione comprende un circuito tampone o buffer per bufferizzare un segnale di ingresso, un circuito di pompaggio di alta tensione per produrre una tensione desiderata in risposta ad un segnale di uscita del circuito buffer ed un circuito di disconnessione per scollegare o di sconnettere il circuito buffer ed il circuito di pompaggio di alta tensione quando la tensione di uscita del circuito buffer è la tensione di sorgente e quella del circuito di pompaggio di alta tensione è una tensione alta, in cui il circuito di disconnessione comprende un transistor di riempimento o arricchimento ed un transistor di svuotamento collegati in serie, le porte dei transistor essendo collegate comunemente alla tensione di sorgente.
ITMI922927A 1991-12-28 1992-12-22 Circuito di commutazione di alta tensione in particolare per dispositivi di memoria a semiconduttori. IT1256217B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910024801A KR940008206B1 (ko) 1991-12-28 1991-12-28 고전압 스위치 회로

Publications (3)

Publication Number Publication Date
ITMI922927A0 ITMI922927A0 (it) 1992-12-22
ITMI922927A1 ITMI922927A1 (it) 1994-06-22
IT1256217B true IT1256217B (it) 1995-11-29

Family

ID=19326362

Family Applications (1)

Application Number Title Priority Date Filing Date
ITMI922927A IT1256217B (it) 1991-12-28 1992-12-22 Circuito di commutazione di alta tensione in particolare per dispositivi di memoria a semiconduttori.

Country Status (7)

Country Link
JP (1) JP2677747B2 (it)
KR (1) KR940008206B1 (it)
DE (1) DE4242801C2 (it)
FR (1) FR2685807B1 (it)
GB (1) GB2262850B (it)
IT (1) IT1256217B (it)
TW (1) TW209926B (it)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4128763B2 (ja) 2000-10-30 2008-07-30 株式会社東芝 電圧切り替え回路
KR100725993B1 (ko) * 2005-12-28 2007-06-08 삼성전자주식회사 누설 전류를 방지하는 로우 디코더 회로 및 이를 구비하는반도체 메모리 장치
JP4909647B2 (ja) 2006-06-02 2012-04-04 株式会社東芝 不揮発性半導体記憶装置
KR20150121288A (ko) * 2014-04-17 2015-10-29 에스케이하이닉스 주식회사 고전압 스위치 회로 및 이를 포함하는 비휘발성 메모리

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5541030B2 (it) * 1972-02-09 1980-10-21
US4511811A (en) * 1982-02-08 1985-04-16 Seeq Technology, Inc. Charge pump for providing programming voltage to the word lines in a semiconductor memory array
JPS58151124A (ja) * 1982-03-04 1983-09-08 Ricoh Co Ltd レベル変換回路
US4672241A (en) * 1985-05-29 1987-06-09 Advanced Micro Devices, Inc. High voltage isolation circuit for CMOS networks
US4689495A (en) * 1985-06-17 1987-08-25 Advanced Micro Devices, Inc. CMOS high voltage switch
JPH0748310B2 (ja) * 1987-04-24 1995-05-24 株式会社東芝 半導体集積回路
US4888738A (en) * 1988-06-29 1989-12-19 Seeq Technology Current-regulated, voltage-regulated erase circuit for EEPROM memory
DE3934303C2 (de) * 1988-10-15 2001-01-25 Sony Corp Adreßdecoder für nichtflüchtige Speicher

Also Published As

Publication number Publication date
GB2262850A (en) 1993-06-30
ITMI922927A0 (it) 1992-12-22
ITMI922927A1 (it) 1994-06-22
TW209926B (it) 1993-07-21
FR2685807A1 (fr) 1993-07-02
FR2685807B1 (fr) 1995-11-03
GB2262850B (en) 1996-04-17
GB9226862D0 (en) 1993-02-17
KR940008206B1 (ko) 1994-09-08
KR930014615A (ko) 1993-07-23
JPH05259473A (ja) 1993-10-08
JP2677747B2 (ja) 1997-11-17
DE4242801A1 (it) 1993-07-01
DE4242801C2 (de) 2000-02-10

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Legal Events

Date Code Title Description
0001 Granted
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19961223