GB2262850A - Switching circuit for eeprom - Google Patents
Switching circuit for eeprom Download PDFInfo
- Publication number
- GB2262850A GB2262850A GB9226862A GB9226862A GB2262850A GB 2262850 A GB2262850 A GB 2262850A GB 9226862 A GB9226862 A GB 9226862A GB 9226862 A GB9226862 A GB 9226862A GB 2262850 A GB2262850 A GB 2262850A
- Authority
- GB
- United Kingdom
- Prior art keywords
- high voltage
- transistor
- disconnecting
- switching circuit
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000005086 pumping Methods 0.000 claims description 25
- 239000004065 semiconductor Substances 0.000 claims description 8
- 230000003139 buffering effect Effects 0.000 claims description 6
- 230000004044 response Effects 0.000 claims description 6
- 230000015556 catabolic process Effects 0.000 description 6
- 238000000034 method Methods 0.000 description 4
- 230000005684 electric field Effects 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 230000010355 oscillation Effects 0.000 description 2
- 230000000737 periodic effect Effects 0.000 description 2
- 230000001066 destructive effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H01L27/0883—
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/12—Programming voltage switching circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/143—Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels ; Switching between alternative supplies
-
- H01L27/0251—
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/06—Modifications for ensuring a fully conducting state
- H03K17/063—Modifications for ensuring a fully conducting state in field-effect transistor switches
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/10—Modifications for increasing the maximum permissible switched voltage
- H03K17/102—Modifications for increasing the maximum permissible switched voltage in field-effect transistor switches
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
- H03K17/693—Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Logic Circuits (AREA)
- Read Only Memory (AREA)
- Semiconductor Integrated Circuits (AREA)
- Electronic Switches (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Non-Volatile Memory (AREA)
- Dc-Dc Converters (AREA)
- Semiconductor Memories (AREA)
Description
2262850 SWITCHING CIRCUIT The present invention relates to semiconductor
memory devices, and more particularly to voltage switching circuits therefor.
For an EEPROM (Electrically Erasable Programmable Read Only Memory), a destructive voltage across a transistor is a serious problem caused by a high voltage produced in a memory integrated circuit when programming or erasing data.
A conventional high voltage switching circuit shown in Figure 1 of the accompanying diagrammatic drawings includes a NAND gate 10 for buffering input signals, a depletion type transistor 12 having a channel connected between an output terminal of NAND gate 10 and a first node 11 for disconnecting a source voltage from a high voltage, and a high voltage pumping circuit 14 connected between the first node 11 and an output terminal for producing either a high voltage or a ground voltage in response to the input signals. The high voltage pumping circuit 14 further includes a first NMOS transistor 16 having a channel connected between a high voltage supply Vpp and a second node 22 and further having a gate connected to the first node 11, a second NMOS transistor 18 having a channel connected between the first and second nodes 11 and 22 and further having a gate connected to the second node 22, and a third NMOS transistor 25 having a gate connected to the second node 22 and a channel having both terminals commonly connected to each other.
In a high voltage switching operation, the input terminal Vpp is supplied with a high voltage, a first input (DD of NAND gate 10 is maintained at a high state, a gate input (DP of depletion transistor 12 is at a low state, and an input (D of the third NMOS transistor 25 makes periodic oscillations. In this case, if a second input of NAND gate 10 receives a signal having a high level, the output of NAND gate 10 is at a ground level and, therefore, so is first node 11.
However, if the second input of NAND gate 10 receives a signal having a low level, the output of NAND gate 10 is at high level. Depletion transistor 12 is turned on to provide the first node 11 with a voltage obtained by subtracting the threshold voltage of transistor 12 from the high level of NAND gate 10, thereby driving the high voltage pumping circuit 14. Also, depletion transistor 12 disconnects the output voltage of NAND gate 10 from the high voltage of first node 11. In this case, the gate of transistor 12 is provided with a ground voltage. If the gate of depletion transistor 12 is provided with a source voltage Vcc, a short circuit operation occurs between high voltage supply Vpp and source voltage Vcc,so as not to produce a high voltage on the output terminal.
In a high voltage switching operation, a break-down voltage across depletion transistor 12 occurs due to an electric field between the gate and drain of depletion transistor 12 when the output terminal is raised to a high voltage and the gate of depletion transistor 12 is grounded. Hence, a high voltage at the output terminal may not be produced above a given vaiue, in order to prevent this problem. The problem can be resolved through the manufacturing process. However, the size of the semiconductor integrated circuit is unavoidably increased, making it difficult to achieve a highly integrated circuit.
Preferred embodiments of the present invention aim to provide a high voltage switching circuit for a semiconductor memory device that produces a desired high voltage.
According to one aspect of the present invention, a high voltage switching circuit for a semiconductor memory device includes a depletion type transistor and enhancement type transistor connected in series. Their gates are connected to a source voltage, whereby the intensity of the electric field across the gate and drain of the transistors is reduced, thereby raising the 10 break-down voltage.
According to another aspect of the present invention, there is provided a high voltage switching circuit comprising:
a buffer means for buffering an input signal; a high voltage pumping means for producing a given voltage in response to an output signal of said buffer means; and a disconnecting means connected between said buffer means and said high voltage pumping means, for disconnecting said buffer means and high voltage pumping circuit when said output voltage of said buffer means is a source voltage and the output signal of said high voltage pumping circuit is a high voltage, said disconnecting means comprising an enhancement transistor and depletion transistor connected in series, gates of said enhancement transistor and said depletion transistor being commonly connected to said source voltage.
Preferably, said buffer means is an inverter, NAND gate or NOR gate.
Preferably, said enhancement and depletion transistors comprise ad acent channels formed below a common gate. j According to a further aspect of the present invention, there is provided a high voltage switching circuit comprising:
a buffer means for buffering an input signal; a high voltage pumping circuit for producing a desired voltage in response to an output signal of said buffer means; and a disconnecting transistor means connected between said buffer means and said high voltage pumping circuit for disconnecting said buffer means and said high voltage pumping circuit when said output voltage of said buffer means is a source voltage and the output voltage of said high voltage pumping circuit is a high voltage, wherein a first channel region adjacent to a source of said disconnecting transistor means has a different conductive type from a channel region adjacent to a drain of said disconnecting transistor means.
Preferably, said disconnecting transistor means comprises a depletion transistor and an enhancement transistor, a channel of said depletion transistor being said first channel region, a channel of said enhancement transistor being said second channel region.
Preferably, a gate of said disconnecting transistor means is connected with said source voltage.
Preferably, said depletion transistor of said disconnecting transistor means is connected with an output terminal of said high voltage pumping circuit.
The invention extends to a semiconductor memory device provided with a high voltage switching circuit according to any of the preceding aspects of the invention.
For a better understanding of the invention and to show how the same 10 may be carried into effect, reference will now be made, by way of example, to Figures 2 to 5 of the accompanying diagrammatic drawings, in which:
Figure 2 is a schematic diagram of one example of a circuit according to an embodiment of the present invention; is Figure 3 is a layout for producing the circuit of Figure 2; Figure 4 is a cross sectional view taken along line A-A' of Figure 3; and Figure 5 is a graph comparing breakdown voltages characteristic of enhancement and depletion transistors according to the circuit of Figure 2 with that of conventional circuits.
A high voltage switching circuit shown in Figure 2 includes an inverting circuit 30 for buffering an input control signal, a high voltage pumping circuit 40 for producing a high or ground voltage in response to output signals from inverting circuit 30 and a disconnecting circuit 50 for electrically disconnecting the inverting circuit 30 from high voltage pumping circuit 40. In this case, inverting circuit 30 may be substituted by a NAND gate or NOR gate. Disconnecting circuit 50 includes a depletion type transistor 36 and an enhancement type transistor 34.
is In high voltage switching operation, an input terminal Vpp is provided with a high voltage, and input D makes periodic oscillations. If the control input of inverting circuit 30 is high, first, second and third nodes 31, 32 and 33 become low, so that high voltage pumping circuit 40 is not driven.
However, if the control input of inverting circuit 30 is low, the first node 31 becomes high, and the second node 32 is dropped from a source voltage Vcc to a voltage Vcc-VTE that is obtained by subtracting a threshold voltage VTE of enhancement transistor 34 from source voltage Vcc. The voltage Vcc-VTE drives high voltage pumping circuit 40 to raise the voltage level of output terminal, i.e. third node 33 is raised to high voltage Vpp. The third node 33 and voltage source node 31 are electrically disconnected by enhancement mode transistor 34.
Referring to Figure 3, a device region 60, a polysilicon layer 62 for a 1 gate extending in a given direction over device region 60, and a depletion ion implantation region 64 overlapping a portion of polysilicon layer 62 in device region 60 are formed in a semiconductor substrate.
Device region 60 shown in Figure 4 is limited by a field oxide layer
70, and includes a source 66 and a drain 68 separated from each other by a channel region, and gate 62 of polysilicon formed over the channel region.
Depletion mode transistor 36 and enhancement mode transistor 34 are formed in the channel region.
With reference to Figure 5, the breakdown voltage characteristics of enhancement and depletion transistors according to the circuit of Figure 2 are compared with those of conventional circuits. Vertical and horizontal axes represent the current and voltage respectively between a drain and source. A line indicated by reference numeral 71 represents a characteristic curve of enhancement NMOS transistor 34 having the gate and source connected to a ground voltage. A line indicated by reference numeral 73 represents a characteristic curve of a floating-source enhancement NMOS transistor having a gate connected to the source voltage according to prior art. The line indicated by reference numeral 75 represents a characteristic curve of a depletion NMOS transistor having a gate connected to a ground voltage and a source to the source voltage according to prior arL The line indicated by reference numeral 77 represents a characteristic curve of floating- source depletion transistor 36 having its gate connected to source voltage. Thus, it may be seen apparent that the highest transistor breakdown voltage is obtained by the circuit of Figure 2.
As stated above, the illustrated switching circuit employs a disconnecting circuit for disconnecting the high voltage of the output terminal and the output voltage of the buffer circuit. The switching circuit includes enhancement and depletion transistors having channels connected in series and gates commonly provided with the source voltage. Thus, electric fields applied to the gate and drain of the transistors are lessened when the output voltage is raised to a high level. As a result, the break-down voltage of the transistors is increased so as to produce the desired high voltage at the output terminal of the circuit.
Furthermore, since enhancement and depletion transistors are simultaneously formed in one channel, the layout area of the integrated circuit may be reduced, to achieve a semiconductor memory device having high density. Consequently, a high voltage switching circuit having a maximum 5 high voltage in a minimum size integrated circuit is obtained.
While a preferred embodiment of the invention has been shown and described in detail, it will be apparent to those skilled in the art that modifications in detail may be made without departing from the spirit and scope of the invention.
The term "ground potential" (or like terms such as "ground voltage" or "earth" potential or voltage) is used conveniently in this specification to denote a reference potential. As will be understood by those skilled in the art, although such reference potential may typically be zero potential, it is not essential that it is so, and may be a reference potential other than zero.
The reader's attention is directed to all papers and documents which are filed concurrently with or previous to this specification in connection with this application and which are open to public inspection with this specification, and the contents of all such papers and documents are incorporated herein by reference.
All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and/or all of the steps of any method or process so disclosed, may be combined in any combination, except combinations where at least some of such features and/or steps are mutually exclusive.
1 Each feature disclosed in this specification (including any accompanying claims, abstract and drawings), may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Thus, unless expressly stated otherwise, each feature disclosed is one example only of a generic series of equivalent or similar features.
The invention is not restricted to the details of the foregoing embodiment(s). The invention extends to any novel one, or any novel combination, of the features disclosed in this specification (including any accompanying claims, abstract and drawings), or to any novel one, or any novel combination, of the steps of any method or process so disclosed.
Claims (9)
1. A high voltage switching circuit comprising:
a buffer means for buffering an input signal; a high voltage pumping means for producing a given voltage in response to an output signal of said buffer means; and a disconnecting means connected between said buffer means and said high voltage pumping means, for disconnecting said buffer means and high voltage pumping circuit when said output voltage of said buffer means is a source voltage and the output signal of said high voltage pumping circuit is a high voltage, said disconnecting means comprising an enhancement transistor and depletion transistor connected in series, gates of said enhancement transistor and said depletion transistor being commonly connected to said source voltage.
2. A high voltage switching circuit according to claim 1, wherein said buffer means is an inverter, NAND gate or NOR gate.
3. A high voltage switching circuit according to claim 1 or 2, wherein said enhancement and depletion transistors comprise adjacent channels formed below a common gate.
4. A high voltage switching circuit comprising:
a buffer means for buffering an input signal; 11 - a high voltage pumping circuit for producing a desired voltage in response to an output signal of said buffer means; and a disconnecting transistor means connected between said buffer means and said high voltage pumping circuit for disconnecting said buffer means and said high voltage pumping circuit when said output voltage of said buffer means is a source voltage and the output voltage of said high voltage pumping circuit is a high voltage, wherein a first channel region adjacent to a source of said disconnecting transistor means has a different conductive type from a channel region adjacent to a drain of said disconnecting transistor means.
5. A high voltage switching circuit according to claim 4, wherein said disconnecting transistor means comprises a depletion transistor and an enhancement transistor, a channel of said depletion transistor being said first channel region, a channel of said enhancement transistor being said second channel region.
6. A high voltage switching circuit according to claim 4 or 5, wherein a gate of said disconnecting transistor means is connected with said source voltage.
7. A high voltage switching circuit according to claim 5 or claims 5 and 6, wherein said depletion transistor of said disconnecting transistor means is connected with an output terminal of said high voltage pumping circuit.
8. A high voltage switching circuit substantially as hereinbefore described with reference to Figures 2 to 6 of the accompanying drawings.
9. A semiconductor memory device provided with a high voltage switching circuit according to any of the preceding claims.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB9518262A GB2291296B (en) | 1991-12-28 | 1992-12-23 | Switching circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910024801A KR940008206B1 (en) | 1991-12-28 | 1991-12-28 | High voltage switch circuit |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB9226862D0 GB9226862D0 (en) | 1993-02-17 |
| GB2262850A true GB2262850A (en) | 1993-06-30 |
| GB2262850B GB2262850B (en) | 1996-04-17 |
Family
ID=19326362
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB9226862A Expired - Fee Related GB2262850B (en) | 1991-12-28 | 1992-12-23 | Switching circuit |
Country Status (7)
| Country | Link |
|---|---|
| JP (1) | JP2677747B2 (en) |
| KR (1) | KR940008206B1 (en) |
| DE (1) | DE4242801C2 (en) |
| FR (1) | FR2685807B1 (en) |
| GB (1) | GB2262850B (en) |
| IT (1) | IT1256217B (en) |
| TW (1) | TW209926B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4128763B2 (en) | 2000-10-30 | 2008-07-30 | 株式会社東芝 | Voltage switching circuit |
| KR100725993B1 (en) * | 2005-12-28 | 2007-06-08 | 삼성전자주식회사 | Row decoder for preventing leakage current and semiconductor memory device having the same |
| JP4909647B2 (en) | 2006-06-02 | 2012-04-04 | 株式会社東芝 | Nonvolatile semiconductor memory device |
| KR20150121288A (en) * | 2014-04-17 | 2015-10-29 | 에스케이하이닉스 주식회사 | High-voltage switch circuit and non-volatile memory including the same |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0204499A2 (en) * | 1985-05-29 | 1986-12-10 | Advanced Micro Devices, Inc. | High voltage isolation circuit for CMOS networks |
| US4689495A (en) * | 1985-06-17 | 1987-08-25 | Advanced Micro Devices, Inc. | CMOS high voltage switch |
| GB2220811A (en) * | 1988-06-29 | 1990-01-17 | Seeq Technology Inc | Current-regulated, voltage-regulated erase circuit for eeprom-memory cells |
| US5099143A (en) * | 1988-10-15 | 1992-03-24 | Sony Corporation | Dual voltage supply circuit with multiplier-controlled transistor |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5541030B2 (en) * | 1972-02-09 | 1980-10-21 | ||
| US4511811A (en) * | 1982-02-08 | 1985-04-16 | Seeq Technology, Inc. | Charge pump for providing programming voltage to the word lines in a semiconductor memory array |
| JPS58151124A (en) * | 1982-03-04 | 1983-09-08 | Ricoh Co Ltd | Level converting circuit |
| JPH0748310B2 (en) * | 1987-04-24 | 1995-05-24 | 株式会社東芝 | Semiconductor integrated circuit |
-
1991
- 1991-12-28 KR KR1019910024801A patent/KR940008206B1/en not_active IP Right Cessation
-
1992
- 1992-10-21 TW TW081108372A patent/TW209926B/zh not_active IP Right Cessation
- 1992-11-12 FR FR9213607A patent/FR2685807B1/en not_active Expired - Fee Related
- 1992-12-17 DE DE4242801A patent/DE4242801C2/en not_active Expired - Fee Related
- 1992-12-22 IT ITMI922927A patent/IT1256217B/en active IP Right Grant
- 1992-12-23 GB GB9226862A patent/GB2262850B/en not_active Expired - Fee Related
- 1992-12-25 JP JP34656292A patent/JP2677747B2/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0204499A2 (en) * | 1985-05-29 | 1986-12-10 | Advanced Micro Devices, Inc. | High voltage isolation circuit for CMOS networks |
| US4689495A (en) * | 1985-06-17 | 1987-08-25 | Advanced Micro Devices, Inc. | CMOS high voltage switch |
| GB2220811A (en) * | 1988-06-29 | 1990-01-17 | Seeq Technology Inc | Current-regulated, voltage-regulated erase circuit for eeprom-memory cells |
| US5099143A (en) * | 1988-10-15 | 1992-03-24 | Sony Corporation | Dual voltage supply circuit with multiplier-controlled transistor |
Also Published As
| Publication number | Publication date |
|---|---|
| ITMI922927A1 (en) | 1994-06-22 |
| JPH05259473A (en) | 1993-10-08 |
| DE4242801A1 (en) | 1993-07-01 |
| GB2262850B (en) | 1996-04-17 |
| TW209926B (en) | 1993-07-21 |
| KR930014615A (en) | 1993-07-23 |
| ITMI922927A0 (en) | 1992-12-22 |
| FR2685807B1 (en) | 1995-11-03 |
| GB9226862D0 (en) | 1993-02-17 |
| JP2677747B2 (en) | 1997-11-17 |
| DE4242801C2 (en) | 2000-02-10 |
| IT1256217B (en) | 1995-11-29 |
| FR2685807A1 (en) | 1993-07-02 |
| KR940008206B1 (en) | 1994-09-08 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 20111223 |