KR940008206B1 - High voltage switch circuit - Google Patents
High voltage switch circuit Download PDFInfo
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- KR940008206B1 KR940008206B1 KR1019910024801A KR910024801A KR940008206B1 KR 940008206 B1 KR940008206 B1 KR 940008206B1 KR 1019910024801 A KR1019910024801 A KR 1019910024801A KR 910024801 A KR910024801 A KR 910024801A KR 940008206 B1 KR940008206 B1 KR 940008206B1
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- high voltage
- transistor
- switch circuit
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- 230000003139 buffering effect Effects 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 abstract description 5
- 230000015556 catabolic process Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 230000005684 electric field Effects 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 230000000903 blocking effect Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000005283 ground state Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 238000005086 pumping Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/0883—Combination of depletion and enhancement field effect transistors
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/12—Programming voltage switching circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/143—Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels ; Switching between alternative supplies
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/06—Modifications for ensuring a fully conducting state
- H03K17/063—Modifications for ensuring a fully conducting state in field-effect transistor switches
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/10—Modifications for increasing the maximum permissible switched voltage
- H03K17/102—Modifications for increasing the maximum permissible switched voltage in field-effect transistor switches
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
- H03K17/693—Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Logic Circuits (AREA)
- Read Only Memory (AREA)
- Semiconductor Integrated Circuits (AREA)
- Electronic Switches (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Non-Volatile Memory (AREA)
- Dc-Dc Converters (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
제1도는 종래의 회로도.1 is a conventional circuit diagram.
제2도는 본 발명에 따른 회로도.2 is a circuit diagram according to the present invention.
제3도는 본 발명에 따른 레이아웃도.3 is a layout diagram according to the present invention.
제4도는 본 발명에 따른 단면도.4 is a cross-sectional view according to the present invention.
제5도는 트랜지스터의 파괴전압 특성비교도.5 is a breakdown voltage characteristic comparison of transistors.
본 발명은 반도체 메모리장치에 관한 것으로, 특히 고전압 스위치회로에 관한 것이다.The present invention relates to a semiconductor memory device, and more particularly to a high voltage switch circuit.
EEPROM(Electrically Erasable Programable Read Only Memory)의 경우 프로그램 또는 소거시 칩내부에서 고전압이 발생하게 되며 이때 트랜지스터의 파괴전압이 심각한 문제로 대두된다.In the case of EEPROM (Electrically Erasable Programmable Read Only Memory), high voltage is generated inside the chip during programming or erasing, and the breakdown voltage of the transistor becomes a serious problem.
이와 관련하여 종래에 제시된 고전압 스위치회로가 논문 'IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 26, NO.4, APRIL 1991'의 페이지 492~496 사이에 "A 4-Mb NAND EEPROM with Tight Programmed VtDistribution"라는 제목으로 개시되어 있다.In this regard, a conventional high voltage switch circuit is proposed in the paper 'IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 26, NO.4, APRIL 1991 'has been disclosed in pages 492 ~ titled between 496 "A 4-Mb NAND EEPROM with Tight Programmed V t Distribution".
제1도는 상기 논문에 개시된 고전압 스위치회로를 보여주는 도면이다. 상기 도면에 도시된 바와 같이 입력을 버퍼링하는 낸드게이트(10)와, 상기 낸드게이트(10)의 출력과 제1노드(11)에 채널이 연결되어 고전압과 전원전압을 차단시켜 주는 디플리션(depletion)형 트랜지스터(12)와, 상기 제1노드(11)와 출력단자에 연결되어 입력신호에 따라 고전압 또는 접지전압을 출력하는 고전압 펌프회로부(14)로 구성된다. 상기 고전압 펌프회로부(14)는, 고전압(Vpp)단과 제2노드(22) 사이에 채널이 연결되고 상기 제1노드(11)에 게이트가 연결된 제1n모오스 트랜지스터(16)와, 상기 제2노드(22)와 제1노드(11)에 채널이 연결되고 상기 제2노드(22)에 게이트가 연결된 제2n모오스 트랜지스터(18)와, 상기 제2노드(22)에 게이트가 연결되고 채널의 양단이 공통으로 묶인 제3n모오스 캐패시터(30)로 구성된다. 상기 고전압 스위치회로의 동작시 Vpp에 고전압이 인가되고 낸드게이트(10)의 일입력인D는 전원전압(Vcc)레벨의 "하이(high)"상태로 유지되며 디플리션형 트랜지스터(12)의 게이트입력인p는 "로우"상태로 유지되고 제3n모오스 트랜지스터(20)의R입력은 일정주기를 갖고 발진하게 된다. 이와 같은 구성에서, 각 신호들은 상기 논문에 언급되어 있으며, 이를 살펴보면R은 오실레이터(oscillator)의 출력신호로서 고전압을 펌핑시키기 위한 발진클럭이고,p는 프로그램(program)동작시 프로그램을 진행시키기 위한 신호이며,D는 낸드게이트(10)의 방전동작을 인에이블시키기 위한 디스차아지(discharge)신호이다. 그리고 후술되는 설명중에서 전원전압은 Vcc레벨이며, 고전압은 상기 전원전압 Vcc레벨 이상의 승압전압을 의미한다.1 is a view showing a high voltage switch circuit disclosed in the paper. As shown in the figure, a NAND gate 10 buffering an input, a channel connected to an output of the NAND gate 10 and a first node 11 to block high and power voltages ( a high voltage pump circuit unit 14 connected to the depletion type transistor 12 and the first node 11 and the output terminal to output a high voltage or a ground voltage according to an input signal. The high voltage pump circuit unit 14 includes a first n-MOS transistor 16 having a channel connected between a high voltage Vpp terminal and a second node 22 and a gate connected to the first node 11, and the second node. A second n-MOS transistor 18 having a channel connected to the first node 11 and a second node 22 and a gate connected to the second node 22, and a gate connected to the second node 22 and connected to both ends of the channel. The third n-mode capacitors 30 are commonly tied together. During operation of the high voltage switch circuit, a high voltage is applied to Vpp and is a single input of the NAND gate 10. D is maintained at the "high" state of the power supply voltage (Vcc) level and is a gate input of the depletion transistor 12. p remains " low " and the " n " The R input will oscillate with a certain period. In such a configuration, each of the signals is mentioned in the above paper. R is an output signal of the oscillator (oscillator) is an oscillation clock for pumping high voltage, p is a signal to advance the program during program operation, D is a discharge signal for enabling the discharge operation of the NAND gate 10. In the following description, the power supply voltage is at the Vcc level, and the high voltage means a boosted voltage of at least the power supply voltage Vcc.
상기한 조건에서 낸드게이트(10)의 타입력단으로 전원전압(Vcc)레벨의 "하이"상태가 입력되면 상기 낸드게이트(10)의 출력은 접지상태가 된다. 그에 따라 제1노드(11)의 전압상태 역시 접지상태가 된다. 한편 상기 낸드게이트(10)의 타입력으로 "로우" 상태가 입력되면 상기 낸드게이트(10)의 출력은 전원전압(Vcc)레벨의 "하이"상태가 된다. 그에 따라 디플리션형 트랜지스터(12)가 턴온되어 상기 제1노드(11)에는 전원전압(Vcc)레벨의 "하이"상태에서 상기 트랜지스터(12)의 드레쉬홀드(threshold)전압을 뺀 전압상태가 인가됨에 의해 상기 고전압 펌프회로부(14)가 동작하게 된다. 그 결과 상기 제1노드(11)의 전압은 고전압레벨의 "하이"상태가 된다. 여기서 상기 디플리션형 트랜지스터(12)는 낸드게이트(10) 출력단의 전원전압(Vcc)(이는 도면상에는 낸드게이트로 나타나 있지만, 당 기술분야에 주지의 사실인 바와 같이 낸드게이트를 구성 및 실현하는 것은 전원전압단(Vcc)과 접지단 사이에 채널이 연결되는 트랜지스터들이며, 이 트랜지스터들의 전원전압(Vcc)단을 의미한다.)과 제1노드(11)의 고전압을 전기적으로 분리시켜 주는 역할을 한다. 이때 상기 트랜지스터(12)의 게이트에는 반드시 접지전압이 인가되어야 한다. 만약 게이트전위가 전원전압(Vcc)이면 고전압과 전원전압(Vcc)이 전기적으로 쇼트되어 출력단에 고전압이 출력되지 않는다.When the "high" state of the power supply voltage (Vcc) level is input to the type force terminal of the NAND gate 10 under the above conditions, the output of the NAND gate 10 is grounded. Accordingly, the voltage state of the first node 11 also becomes a ground state. On the other hand, when the "low" state is input by the type force of the NAND gate 10, the output of the NAND gate 10 is a "high" state of the power supply voltage (Vcc) level. As a result, the depletion transistor 12 is turned on, and the first node 11 has a voltage state obtained by subtracting the threshold voltage of the transistor 12 from the high state of the power supply voltage Vcc level. The high voltage pump circuit unit 14 is operated by being applied. As a result, the voltage of the first node 11 is in the "high" state of the high voltage level. Here, the depletion transistor 12 is a power supply voltage Vcc of the output terminal of the NAND gate 10 (this is shown as a NAND gate in the drawing, but it is well known in the art to construct and implement a NAND gate. Channels are connected between the power supply voltage terminal (Vcc) and the ground terminal, which means the power supply voltage (Vcc) of these transistors) and the high voltage of the first node (11) to electrically separate. . At this time, the ground voltage must be applied to the gate of the transistor 12. If the gate potential is the power supply voltage Vcc, the high voltage and the power supply voltage Vcc are electrically shorted so that a high voltage is not output to the output terminal.
상기한 바와 같이 고전압 스위치회로 동작시 디플리션형 트랜지스터의 게이트가 접지됨에 따라 출력단이 고전압으로 상승할때 게이트와 드레인에 인가되는 전기장에 의하여 브레이크 다운(break down)이 발생하게 된다. 그리하여, 상기 출력단에서 소정전압 이상의 고전압이 발생될 수 없는 문제점이 있었다.As described above, when the gate of the depletion type transistor is grounded during the operation of the high voltage switch circuit, breakdown occurs due to an electric field applied to the gate and the drain when the output terminal rises to a high voltage. Thus, there is a problem that a high voltage above a predetermined voltage cannot be generated at the output terminal.
상기 문제점을 제조공정을 통해 해결하고자 할 경우 반도체 소자의 스케일 다운(scale down)이 어렵게 되어 결국 기억소자를 고집적화하기 어렵게 된다.When the above problem is to be solved through a manufacturing process, it is difficult to scale down the semiconductor device, which makes it difficult to integrate the memory device.
따라서 본 발명의 목적은 고전압 스위치회로에 있어서 상기 회로의 출력단에서 희망하는 고전압 출력을 얻을 수 있는 고전압 스위치회로를 제공함에 있다.Accordingly, an object of the present invention is to provide a high voltage switch circuit capable of obtaining a desired high voltage output at an output terminal of the circuit in a high voltage switch circuit.
상기한 바와 같은 본 발명의 목적을 달성하기 위하여 고전압이 인가되는 부위에 각각의 게이트가 전원전압에 접속된 디플리션형 트랜지스터와 인핸스먼트형 트랜지스터를 직렬로 접속하여 게이트와 트레인간의 전기장의 세기를 완화시킴에 의해 브레이크 다운 전압을 회로적으로 상승시킴을 특징으로 한다.In order to achieve the object of the present invention as described above, the depletion type transistor and the enhancement type transistor in which each gate is connected to the power supply voltage are connected in series to a portion where high voltage is applied to alleviate the electric field strength between the gate and the train. By increasing the breakdown voltage in a circuit.
이하 본 발명의 바람직한 실시예를 첨부한 도면을 참조하여 상세히 설명한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
제2도는 본 발명에 따른 고전압 스위치회로도이다.2 is a high voltage switch circuit diagram according to the present invention.
상기 도면에 도시된 바와 같이 본 발명에 의한 고전압 스위치회로는, 제어신호를 입력으로 하여 버퍼링하는 반전수단(30)과, 상기 반전수단(30)의 출력을 감지하여 고전압 또는 접지전압을 유지해주는 고전압 펌프회로부(40)와, 전원전압으로 출력되는 반전수단(30)의 출력단과 고전압이 유지되는 출력단을 전기적으로 분리시켜 주기 위한 디커플링수단(50)으로 구성된다. 상기 디커플링수단(50)은 직렬접속된 디플리션형 및 인핸스먼트(enhancement)형 트랜지스터(36)(34)로 이루어진다. 상기 고전압 스위치회로의 동작시 Vpp에 고전압이 인가되고,R입력은 일정주기를 갖고 발진하게 된다. 상기 조건에서 상기 반전수단(30)의 제어입력이 전원전압(Vcc)레벨의 "하이"상태이면 제1, 제2 및 제3노드(31,32,33)는 "로우"상태가 되어 상기 고전압 펌프회로부(40)는 동작하게 않게 된다. 결국 출력단인 상기 제3노드(33)는 "로우"상태를 유지한다. 한편, 상기 반전수단(30)의 제어입력이 "로우"상태이면 상기 제1노드(31)는 전원전압(Vcc)레벨의 "하이"상태가 되고, 상기 제2노드(32)는 상기 "하이"상태에서 상기 인핸스먼트형 트랜지스터(34)의 드레쉬홀드전압(VTE)만큼 강하된 전압상태(Vcc-VTE)가 된다. 상기 Vcc-VTE전압에 의해 고전압 펌프회로부(40)가 동작되어 상기 출력단, 즉 제3노드(33)는 전원전압(Vcc)으로 상승하게 된다. 이때 고전압의 출력단 노드(33)와 전원전압(Vcc) 노드(31)는 상기 인핸스먼트형 트랜지스터(34)에 의해 전기적으로 분리된다.As shown in the figure, the high voltage switch circuit according to the present invention includes a reversal means 30 for buffering a control signal as an input and a high voltage for sensing the output of the reversal means 30 to maintain a high voltage or a ground voltage. And a decoupling means 50 for electrically separating the pump circuit portion 40, the output end of the inverting means 30 outputted from the power supply voltage, and the output end maintaining the high voltage. The decoupling means 50 consists of depletion type and enhancement type transistors 36 and 34 connected in series. High voltage is applied to Vpp during the operation of the high voltage switch circuit, The R input will oscillate with a certain period. Under the above conditions, when the control input of the inverting means 30 is in the "high" state of the power supply voltage Vcc level, the first, second and third nodes 31, 32, and 33 are in the "low" state, and the high voltage The pump circuit portion 40 is not operated. As a result, the third node 33, which is an output terminal, remains in a "low" state. On the other hand, when the control input of the inverting means 30 is in the "low" state, the first node 31 is in the "high" state of the power supply voltage (Vcc) level, and the second node 32 is in the "high" state. In the "state," the voltage state Vcc-V TE is lowered by the threshold voltage V TE of the enhancement transistor 34. The high voltage pump circuit unit 40 is operated by the Vcc-V TE voltage so that the output terminal, that is, the third node 33, rises to the power supply voltage Vcc. At this time, the high voltage output terminal node 33 and the power supply voltage (Vcc) node 31 are electrically separated by the enhancement type transistor 34.
제3도는 본 발명에 따른 디커플링수단의 레이아웃도이다. 반도체기판의 소정영역에 형성된 소자영역(60)과, 상기 소자영역(60) 상부에서 소정방향으로 신장되며 게이트로 이용되는 다결정실리콘층(62)과, 상기 소자영역(60)내에서 상기 다결정실리콘층(62)이 형성된 영역과 소정부분 오버랩되어 형성된 디플리션 이온주입영역(64)을 나타낸다.3 is a layout diagram of the decoupling means according to the invention. A device region 60 formed in a predetermined region of the semiconductor substrate, a polysilicon layer 62 extending in a predetermined direction above the device region 60 and serving as a gate, and the polysilicon in the device region 60. The depletion ion implantation region 64 formed by overlapping a predetermined portion with the region where the layer 62 is formed is shown.
제4도는 상기 제3도의 A-A'선을 자른 단면도로서, 상기 제3도와 같은 명칭에 해당하는 것은 같은 번호를 사용하였다. 필드산화막(66)에 의해 한정되는 소자영역(60)내에 채널영역에 의해 서로 이격되는 소오스 및 드레인(66,68)과 상기 채널영역 상부에 다결정실리콘층으로 형성된 게이트(62)를 나타낸다. 상기 채널영역내에는 디플리션형 트랜지스터(36)와, 인핸스먼트형 트랜지스터(34)가 동시에 형성되어 있다.4 is a cross-sectional view taken along the line A-A 'of FIG. 3, and the same numerals are used to correspond to the same names as in FIG. Source and drain 66 and 68 spaced apart from each other by the channel region in the device region 60 defined by the field oxide film 66 and a gate 62 formed of a polysilicon layer on the channel region. The depletion transistor 36 and the enhancement transistor 34 are formed at the same time in the channel region.
제5도는 트랜지스터의 파괴전압 특성비교도로서, 드레인-소오스간의 전류와 전압을 각각 세로축과 가로축 좌표로 한다. 71은 종래의 게이트 및 소오스가 전원 접지단에 연결된 인핸스먼트형 n모오스 트랜지스터의 특성곡선이고, 73은 종래의 게이트가 전원전압(Vcc)단에 연결되고 소오스가 플로팅된 인핸스먼트형 n모오스 트랜지스터의 특성곡선이다. 그리고 75는 종래의 게이트가 전원접지단에 연결되고 소오스에 전원전압(Vcc)단이 연결된 디플리션형 n모오스 트랜지스터의 특성곡선이고, 77은 본 발명에 따른 게이트가 전원전압(Vcc)단에 연결되고 소오스가 플로팅된 디플리션형 트랜지스터의 특성곡선이다. 상기 도면에서 본 발명에 따른 트랜지스터의 파괴전압이 가장 높음을 알 수 있다.5 is a breakdown voltage characteristic comparison diagram of transistors, in which the current and the voltage between the drain and the source are the vertical axis and the horizontal axis coordinate, respectively. 71 is a characteristic curve of an enhancement n-MOS transistor in which a conventional gate and a source are connected to a power supply ground terminal, and 73 is a characteristic curve of an enhancement n-MOS transistor in which a conventional gate is connected to a power supply voltage (Vcc) terminal and a source is floated. Characteristic curve. 75 is a characteristic curve of a depletioned n-MOS transistor in which a conventional gate is connected to a power supply ground terminal and a power supply voltage (Vcc) is connected to a source, and 77 is a gate connected to a power supply voltage (Vcc) terminal according to the present invention. And a characteristic curve of the depletion transistor with the source floated. In the figure it can be seen that the breakdown voltage of the transistor according to the present invention is the highest.
상술한 바와 같이 본 발명은 고전압 스위치회로에 있어서 출력단의 고전압과 버퍼수단의 출력전압을 차단하기 위한 디커플링수단으로서 채널이 직렬연결된 인핸스먼트형 및 디플리션형 트랜지스터를 형성하여 그 공통게이트에 전원전압(Vcc)을 인가함으로써 고전압 스위치회로의 출력전압이 고전압으로 상승될때 상기 게이트와 드레인에 인가되는 전계가 완화되도록 하였다. 그에 따라 상기 트랜지스터의 브레이크 다운 전압을 회로적으로 상승시킴에 의해 고전압 스위치회로의 출력단에서 원하는 정도의 고전압을 얻을 수 있는 효과가 있다. 게다가 인핸스먼트형 및 디플리션형 트랜지스터를 하나의 채널내에 동시에 형성함에 의해 레이아웃에 대한 부담을 줄일 수 있으며 그에 따른 반도체장치의 고집적화가 가능한 효과도 있다. 그 결과 최소의 칩면적내에서 최대의 고전압을 갖는 고전압 스위치회로를 구현할 수 있다.As described above, the present invention forms an enhancement type and a depletion type transistor in which channels are connected in series as a decoupling means for blocking a high voltage at an output terminal and an output voltage of a buffer means in a high voltage switch circuit, and a power supply voltage is formed at a common gate thereof. By applying Vcc), the electric field applied to the gate and the drain is relaxed when the output voltage of the high voltage switch circuit rises to the high voltage. As a result, by raising the breakdown voltage of the transistor in a circuit, a desired high voltage can be obtained at an output terminal of the high voltage switch circuit. In addition, by forming the enhancement type and depletion type transistors simultaneously in one channel, the burden on the layout can be reduced, and the semiconductor device can be highly integrated. As a result, a high voltage switch circuit having a maximum high voltage in a minimum chip area can be realized.
Claims (6)
Priority Applications (8)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910024801A KR940008206B1 (en) | 1991-12-28 | 1991-12-28 | High voltage switch circuit |
| TW081108372A TW209926B (en) | 1991-12-28 | 1992-10-21 | |
| FR9213607A FR2685807B1 (en) | 1991-12-28 | 1992-11-12 | HIGH VOLTAGE SWITCHING CIRCUIT. |
| DE4242801A DE4242801C2 (en) | 1991-12-28 | 1992-12-17 | High voltage circuit |
| ITMI922927A IT1256217B (en) | 1991-12-28 | 1992-12-22 | HIGH VOLTAGE SWITCHING CIRCUIT IN PARTICULAR FOR SEMICONDUCTOR MEMORY DEVICES. |
| GB9518262A GB2291296B (en) | 1991-12-28 | 1992-12-23 | Switching circuit |
| GB9226862A GB2262850B (en) | 1991-12-28 | 1992-12-23 | Switching circuit |
| JP34656292A JP2677747B2 (en) | 1991-12-28 | 1992-12-25 | High voltage switch circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910024801A KR940008206B1 (en) | 1991-12-28 | 1991-12-28 | High voltage switch circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR930014615A KR930014615A (en) | 1993-07-23 |
| KR940008206B1 true KR940008206B1 (en) | 1994-09-08 |
Family
ID=19326362
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019910024801A KR940008206B1 (en) | 1991-12-28 | 1991-12-28 | High voltage switch circuit |
Country Status (7)
| Country | Link |
|---|---|
| JP (1) | JP2677747B2 (en) |
| KR (1) | KR940008206B1 (en) |
| DE (1) | DE4242801C2 (en) |
| FR (1) | FR2685807B1 (en) |
| GB (1) | GB2262850B (en) |
| IT (1) | IT1256217B (en) |
| TW (1) | TW209926B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4128763B2 (en) | 2000-10-30 | 2008-07-30 | 株式会社東芝 | Voltage switching circuit |
| KR100725993B1 (en) * | 2005-12-28 | 2007-06-08 | 삼성전자주식회사 | Row decoder for preventing leakage current and semiconductor memory device having the same |
| JP4909647B2 (en) | 2006-06-02 | 2012-04-04 | 株式会社東芝 | Nonvolatile semiconductor memory device |
| KR20150121288A (en) * | 2014-04-17 | 2015-10-29 | 에스케이하이닉스 주식회사 | High-voltage switch circuit and non-volatile memory including the same |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5541030B2 (en) * | 1972-02-09 | 1980-10-21 | ||
| US4511811A (en) * | 1982-02-08 | 1985-04-16 | Seeq Technology, Inc. | Charge pump for providing programming voltage to the word lines in a semiconductor memory array |
| JPS58151124A (en) * | 1982-03-04 | 1983-09-08 | Ricoh Co Ltd | Level converting circuit |
| US4672241A (en) * | 1985-05-29 | 1987-06-09 | Advanced Micro Devices, Inc. | High voltage isolation circuit for CMOS networks |
| US4689495A (en) * | 1985-06-17 | 1987-08-25 | Advanced Micro Devices, Inc. | CMOS high voltage switch |
| JPH0748310B2 (en) * | 1987-04-24 | 1995-05-24 | 株式会社東芝 | Semiconductor integrated circuit |
| US4888738A (en) * | 1988-06-29 | 1989-12-19 | Seeq Technology | Current-regulated, voltage-regulated erase circuit for EEPROM memory |
| GB2226727B (en) * | 1988-10-15 | 1993-09-08 | Sony Corp | Address decoder circuits for non-volatile memories |
-
1991
- 1991-12-28 KR KR1019910024801A patent/KR940008206B1/en not_active IP Right Cessation
-
1992
- 1992-10-21 TW TW081108372A patent/TW209926B/zh not_active IP Right Cessation
- 1992-11-12 FR FR9213607A patent/FR2685807B1/en not_active Expired - Fee Related
- 1992-12-17 DE DE4242801A patent/DE4242801C2/en not_active Expired - Fee Related
- 1992-12-22 IT ITMI922927A patent/IT1256217B/en active IP Right Grant
- 1992-12-23 GB GB9226862A patent/GB2262850B/en not_active Expired - Fee Related
- 1992-12-25 JP JP34656292A patent/JP2677747B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| DE4242801C2 (en) | 2000-02-10 |
| GB2262850A (en) | 1993-06-30 |
| DE4242801A1 (en) | 1993-07-01 |
| GB2262850B (en) | 1996-04-17 |
| TW209926B (en) | 1993-07-21 |
| GB9226862D0 (en) | 1993-02-17 |
| FR2685807A1 (en) | 1993-07-02 |
| JP2677747B2 (en) | 1997-11-17 |
| FR2685807B1 (en) | 1995-11-03 |
| JPH05259473A (en) | 1993-10-08 |
| ITMI922927A1 (en) | 1994-06-22 |
| KR930014615A (en) | 1993-07-23 |
| IT1256217B (en) | 1995-11-29 |
| ITMI922927A0 (en) | 1992-12-22 |
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