TW209926B - - Google Patents
Download PDFInfo
- Publication number
- TW209926B TW209926B TW081108372A TW81108372A TW209926B TW 209926 B TW209926 B TW 209926B TW 081108372 A TW081108372 A TW 081108372A TW 81108372 A TW81108372 A TW 81108372A TW 209926 B TW209926 B TW 209926B
- Authority
- TW
- Taiwan
- Prior art keywords
- voltage
- transistor
- power supply
- circuit
- supply circuit
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 claims description 17
- 239000013078 crystal Substances 0.000 claims description 4
- 230000003139 buffering effect Effects 0.000 claims description 3
- 230000002079 cooperative effect Effects 0.000 claims description 2
- 230000004044 response Effects 0.000 claims description 2
- 230000005611 electricity Effects 0.000 claims 2
- 238000010521 absorption reaction Methods 0.000 claims 1
- 230000015556 catabolic process Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000005684 electric field Effects 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 235000018185 Betula X alpestris Nutrition 0.000 description 1
- 235000018212 Betula X uliginosa Nutrition 0.000 description 1
- 235000014443 Pyrus communis Nutrition 0.000 description 1
- 241001233037 catfish Species 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000002309 gasification Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000005086 pumping Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000000153 supplemental effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/0883—Combination of depletion and enhancement field effect transistors
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/12—Programming voltage switching circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/143—Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels ; Switching between alternative supplies
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/06—Modifications for ensuring a fully conducting state
- H03K17/063—Modifications for ensuring a fully conducting state in field-effect transistor switches
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/10—Modifications for increasing the maximum permissible switched voltage
- H03K17/102—Modifications for increasing the maximum permissible switched voltage in field-effect transistor switches
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
- H03K17/693—Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors
Landscapes
- Power Engineering (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Semiconductor Integrated Circuits (AREA)
- Electronic Switches (AREA)
- Logic Circuits (AREA)
- Read Only Memory (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Non-Volatile Memory (AREA)
- Dc-Dc Converters (AREA)
- Semiconductor Memories (AREA)
Description
Μ Ο Α6 Β6 部中央標準局負工消費合作社印製 五、發明説明(1 ) 本發明是有關於半導體記億體裝置,且特別是有藺於 一種半導體記憶體用高電壓開關電路。對EEPROM (可電性抹 除之可程式唯讀記憶體)而言,在規塞(PTOgram)或抹除資料 時,一記憶體樓體電路中所產生的一高電壓,若造成一破 壞件電壓跨在一電晶體h ,便會引起驗重的間題。 圔1所示的傳統半導體記億體用高電壓開關電路包括 一 NAND閛,用來_衝輸入信號;一空乏型電晶體12 ,具 有一通道(chanmil)連接在NAND閛10的一輸入讕、和一第一節 點11之間,闬來將源電壓從一高電壓斷接;以及一高電壓 供能(pumping)電路14,連接在第一節點11、和一輸出端之間 ,用來瓛應輸入信號而產生一高電壓、或一接地電壓。高 電壓供能電路14更包括一第一 NM0S電晶體〗6,其具有一通 道連接在一高電暖供應Vpp、和-第二節點22之間,且具有 —閘極連接到第一節點Γ1 ; 一第二NM0S電晶體〗8 ,其具有 一通道連接在第一和第二節點Π和22之間,且具有一閘極 連接到第二節點22 ;以及包括一第三NMOS電晶體25,其具 有一閘極連接到第二節點22 ,目其通道的兩端彼此連接在 一起〇 在一高半導體記億體用電壓開關操作中,輸入端Vpp被 供給一高電壓,NAND閘的第一輸人<M)被維持在一高狀態 (high state),空乏電晶體12的一閑極輸入0 Η是在一低狀態, 且第三NM0S電晶體25的一輸入φ作週期性振盪。在此例中 ,若Ν_閘1Η的一第二輸\接收具有高位準的信號,那麽 NAND閘10的輸出傜在一接地位準,而且第一節點]〗也因此 -3 - (請先閲讀背面之注意事項再塡寫本頁) .裝. 訂' 本紙張尺度適用中國國家律準(CNS)甲4規格(210 X 297公笼〉 82.1. 20,000 1 ) Α6 Β6 五、發明説明(2 ) 是在接地位準。 然if ’若(WNA閛丨0是接收低位準的信號,那麽NAND閘 10的輸出就是高位準。空乏電晶體12被開敗,以提供NAND 蘭10的高位準減去電晶體12的臨限電壓所得的電壓給第一 節點Π,因而驅動高電睡供能電路14。而目,空乏電晶體 12也將NAND閘10的輸出電靨與第一節點的高電壓斷接。 在此例中,電晶體12的閘極被供應一接地電壓。若空乏電 晶體12的閛極是被供應一源電壓Vcc,在高電壓供應Vpp、和 補電壓Vrc之間會發生一短路操作,以致於在輸出端無法產 生一高電壓„ 在一半導體記憶體用高電壓開關操作中,當輸出端升 到一高電壓,且空乏電晶體丨2的閘極被接地時,由於在空 乏電晶體12的閛榷和汲極之間有一電場,所以有一萌潰電 壓跨在空乏電晶體12上:。因此,在輸出端的一高電蹏不應 高於一預定信,以便避免此問題。此問題雖然可以經由製 造程序加以解決,不過半導體積體電路的尺寸將不可避免 地要邡大,導致很雜達到一高度穑集的電路。 本發明的一目的是要提供一棰半導體記億體裝置的高 電壓開關電路,用來產生一所要旳高電壓。 依照本發明的一特點,一種半導體記憶體裝置的高電 壓開閘電路包括一空乏型電晶體、和加強型電晶體串接在 一起。其閘極連接到一梯電壓,因此跨在電晶體閘極和汲 楝上旳電場強度被降低,故將崩潰電壓拉升〇 為了讓本發明更易於被瞭解,且顯示其可實施性,接 一 4 — ------------------, -----裝------訂----· 錄 (請先閲讀背面之注意事項再塡寫本頁) 濟 部 中 央 標 準 員 工 消 費 合 社 印 製 本紙張尺度適用中國國家標準(CNS)甲4規格(210 X 297公釐〉 82.1. 20,000 經 部 t 央 標 準 員 工 消 費 合 if 社 印 製 ,ο Α6 Β6 五、發明説明(3 ) 下來將參照所附圖式舉例説明。 圖式之簡單説明: 圖1是一種傳統電路的電路圖„ 圖2是依照本發明一實施例的一種電路之電路圖。 圖3是用來產生本發明的電路之一種佈局(layout)。 圖4是沿箸圖3的線A-A’剖開之一剖面圖。 圖5和6是本發明電路的加強和空乏電晶體、與傳統 電路的電晶體之崩潰電壓特性的比較圖。 一種半導體記億體用電歷開開電路顯示於圖2中,且 包括一反相電路3H ,用來緩衝一輪人控制信號;一高電壓 供能電路4«,用來馨應反相電路3H的輸出信號而產生一高 電壓或接地電壓;以及包括一斷接電路50,用來將反相電 路30與高電壓供能電路40作電性斷接。在此例中,反相電 路30 tt可以用一 ΝΑΝΙ)閛、或NOR閘取代。斷接電路5H包括一 空乏型電晶體:》、和一加強型電晶體34。 在半導體記憶體用高電壓開閜操作中,一輸入端VPP被 供應一高電壓,且輸>、0作週期性振盪。若反相電路测的 控制_人是高位準,那麽第一、第二、和第三節點3]、32 和33就蠻為低位準,以致於高電壓供能電路物未被驅動。 不過,若反相電路3B的控制輸人是低位準,那麽第一節點 就變為高位準,而第二節點泣則從一源電壓VCC降至一電 壓Vcc-Vte , Vcr-V™就是將源電囑Vcc減去加強型電晶體34的— 臨限電嘢VTE所得者η電贜VfX-VTE驅動高電囅供能電路职, 以拉孙輪出端的電壓位準,也就是説,第三節鲇33被升到 -5 - 本紙張尺度適用中國國家標準(CNS)甲4規格(210 X 297公釐〉 -------^------------ -----裝------訂 - 丨 {請先閲讀背面之注意事項再塡寫本頁) 82.1. 20,000 五、發明説明(4 ) 高電壓Vpp。第三節黏33 34電性斷接。 _參照圖3,在一 、一閛極的聚矽層似, 以及一空乏離子内植區 62的一部份。 A6 B6 、和電壓源節點31被加強型電晶體 半導體基層上形成有一裝置區域60 以一預定方向延伸過裝置區域60、 域64 ,重#於裝置區域60中聚矽層 {請先閲讀背面之注意事項再塡寫本頁) 括聚矽的 和加強型 請参 崩潰電賴 表汲極和 強梨NM0S 一特性曲 電晶體的 。標示為 知技藝連 性曲線。 閛極依照 以很清楚 如上 接輪出端 路包括加 圖*4所不的裝置區域60被 汲極册,被 在通道 成於通 閛極62 電晶體 照圖5 將與傳 源極之 電晶髒 编。標 閛極依 75的線 接到源 標示為 本發明 地看出 所述, 的高電 強型和 ,形成 34刖形 和6 , 統的電 間的電 34的閘 示為73 照習知 是代表 電壓, 77的線 連接到 本#明 本發明 壓、和 空乏型 區域上 道區域 本發明的加強 比較。 壓。樺 源極連 場氣化層70所 通道區域隔離 〇空乏型 中〇 型和空乏型電晶體之 縱軸和橫軸是分別代 示為71的線是代表加 接到一接地電壓時的 浮動頫極加強型NMQS 電壓時的一恃性曲線 限制,且包 開,以及包 電晶體3(5、 1 ) 1 i 部 t 央 標 準 局 員 工 消 費 合 作 社 印 製 .裝. --雄 路作 流和電 極、和 的線是代表 技藝連接到源 一空乏塑NM0S電晶體的源極依照習 連接到 且閘極 是代表 源電壓 獲得最 的開閜 緩衝器 電晶體 -6 - 一浮動 時的一 高的電 電路利 電路的 ,其通 接地電壓時的一待 源極空乏型電晶體的 特性曲绵。因此,可 晶體崩潰電壓。 用一斷接電路,來斷 輸出電® 道串接在 該開關電 起,且蘭 本紙張尺度適用中國國家標準(CNS>甲4規格(210 X 297公釐) 82.1. 20,000 1ί Α6 Β6 五、發明説明(κ )
D 掻共同被供應源電壓,因此,當輸出電壓被升到~高位準 時,加在電晶體的閘極和汲極之電場便被減弱。故,—電 晶體的崩潰電壓被增加,以便在電路的輸出端上產生所要 的高電壓。 吏且,由於加強型和空乏犁電晶醴是同時形成在—個 通道中,所以積體電路的佈局面積可被縮減,而達成高密 度的半導體記億體裝置。故可以樓得一種半導體記億體用 高電壓開闢電路,在一最小尺寸的積體電路中具有一最大 的高電壓。 雖然本發明像參照一較佳實施例作詳細描述和顯示, 但熟悉此藝者應暸解在不脱離本發明的精神和範圍之下, 仍有許多種變化。 (請先閲讀背面之注意事項再場寫本頁) -—裝. 15 經 中 央 標 準 為 員 X 消 費 合 社 印 製 訂* .線 本紙張尺度適用中國國家標·準(CNS)甲4規格(210 X 297公釐) 82.1. 20,000
Claims (1)
- «濟部中去螵準局員工消费合作杜印轚 Δ7 Β7 C7 D7 六、申請專利範圍 1. 一種半導體記憶體用高電壓開關電路包括: 一缓衝器裝置,用來緩衝一輸入信號; 一高電壓供能裝置,用來轡應該缓衝器的一輸出信號 ,產生一預定電壓;以及 一斷接裝置,連接在該緩衝器裝置、和高電壓供能裝 置之間,用來在該緩衝器裝置的輸出電®是一源電壓,且 該高電壓供能電路的輸出信號是-高電壓時,將該缓衝器 裝置、和高電壓供能電路予以斷接,該斷接裝置包括一加 強型電晶體、和空乏型電晶體串接在一起,該加強型電晶 體、和空乏型電晶體的閘極共同連接到該源電壓。 2. 如申請專利範圍第1項所逑之半導體記億體用高電 壓開關電路,其中該緩衝器裝置是一反相器、NAND閘、或 N(1R 閘。 3. 如申請專利範圍第1項所述之半導體記億體用高電 壓開關電路,其中該加強型和空乏型電晶體包括相鄰的通 道,形成在一共同閛極之下。 4. 一種半導體記億體用高電壓開關電路包括: 一缓衝器裝置,用來緩衝一輸人信號; 一高電歷供能電路,用來镳該缧衝器裝置的一輸出 信號,產生一所要的電壓;以及 一斷接電晶體,達接在該缓衝器裝置、和高電壓供能 電路之間,用來在該缓衝器裝置的輪出電壓是一源電壓, 且該高電壓供能電路的輸出電壓是一高電壓時,將該緩衝 器裝置、和高電壓供能電路予以斷接,其中該斷接電晶體 -8 - 本纸張又度適用中國a家揉準(CNS)甲4规格(210 X 297公货) -—U„-----------------裝------訂 (請先閲讀背面之注意事項再塡寫本頁) 〇 A7 B7 C7 D7 的 電和道 電 極 高、通 c 高 汲 用體一域用 一 體晶第區體 其 億電該道億 於。記型是通記 鄰式體乏道二體 相塱導空通第導 及電半 一 一該半 以導之括的是之 .、 的逑包髏道述 域同所體晶通所 區不 項晶電一 項 道有 4 電型的 5 通具第接乏體第 一 別圍斷空晶圍 第分範該該電範 的,利中,型利 棰域專其體強專 源區請,晶加謓 一 道申路電該申 其通如電型而如 於二5.關強,6. 鄰第 開加域 相一 壓一區 六、申請專利範圍 壓開關電路,其中該斷接電晶體的一閘極連接到該源電壓 〇 0 7·如申請專利範圍第5項所述之半導體記億體用高電 壓開關電路,其中該斷接電晶體的空乏型電晶體偽連接到 該高電壓供能電路的一輪出端。 -------1---------- ------裝------訂 (請先閲讀背面之注意事項再填寫本頁) 經濟部中央揉準局β:工消费合作杜印« 朱紙張中88家標準(CNS)甲4规格(21〇 χ 297公梦)·
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019910024801A KR940008206B1 (ko) | 1991-12-28 | 1991-12-28 | 고전압 스위치 회로 |
Publications (1)
Publication Number | Publication Date |
---|---|
TW209926B true TW209926B (zh) | 1993-07-21 |
Family
ID=19326362
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW081108372A TW209926B (zh) | 1991-12-28 | 1992-10-21 |
Country Status (7)
Country | Link |
---|---|
JP (1) | JP2677747B2 (zh) |
KR (1) | KR940008206B1 (zh) |
DE (1) | DE4242801C2 (zh) |
FR (1) | FR2685807B1 (zh) |
GB (1) | GB2262850B (zh) |
IT (1) | IT1256217B (zh) |
TW (1) | TW209926B (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI615846B (zh) * | 2014-04-17 | 2018-02-21 | 愛思開海力士有限公司 | 高電壓開關電路及包括其之非揮發性記憶體 |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4128763B2 (ja) | 2000-10-30 | 2008-07-30 | 株式会社東芝 | 電圧切り替え回路 |
KR100725993B1 (ko) * | 2005-12-28 | 2007-06-08 | 삼성전자주식회사 | 누설 전류를 방지하는 로우 디코더 회로 및 이를 구비하는반도체 메모리 장치 |
JP4909647B2 (ja) | 2006-06-02 | 2012-04-04 | 株式会社東芝 | 不揮発性半導体記憶装置 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5541030B2 (zh) * | 1972-02-09 | 1980-10-21 | ||
US4511811A (en) * | 1982-02-08 | 1985-04-16 | Seeq Technology, Inc. | Charge pump for providing programming voltage to the word lines in a semiconductor memory array |
JPS58151124A (ja) * | 1982-03-04 | 1983-09-08 | Ricoh Co Ltd | レベル変換回路 |
US4672241A (en) * | 1985-05-29 | 1987-06-09 | Advanced Micro Devices, Inc. | High voltage isolation circuit for CMOS networks |
US4689495A (en) * | 1985-06-17 | 1987-08-25 | Advanced Micro Devices, Inc. | CMOS high voltage switch |
JPH0748310B2 (ja) * | 1987-04-24 | 1995-05-24 | 株式会社東芝 | 半導体集積回路 |
US4888738A (en) * | 1988-06-29 | 1989-12-19 | Seeq Technology | Current-regulated, voltage-regulated erase circuit for EEPROM memory |
DE3934303C2 (de) * | 1988-10-15 | 2001-01-25 | Sony Corp | Adreßdecoder für nichtflüchtige Speicher |
-
1991
- 1991-12-28 KR KR1019910024801A patent/KR940008206B1/ko not_active IP Right Cessation
-
1992
- 1992-10-21 TW TW081108372A patent/TW209926B/zh not_active IP Right Cessation
- 1992-11-12 FR FR9213607A patent/FR2685807B1/fr not_active Expired - Fee Related
- 1992-12-17 DE DE4242801A patent/DE4242801C2/de not_active Expired - Fee Related
- 1992-12-22 IT ITMI922927A patent/IT1256217B/it active IP Right Grant
- 1992-12-23 GB GB9226862A patent/GB2262850B/en not_active Expired - Fee Related
- 1992-12-25 JP JP34656292A patent/JP2677747B2/ja not_active Expired - Fee Related
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI615846B (zh) * | 2014-04-17 | 2018-02-21 | 愛思開海力士有限公司 | 高電壓開關電路及包括其之非揮發性記憶體 |
Also Published As
Publication number | Publication date |
---|---|
GB2262850A (en) | 1993-06-30 |
ITMI922927A0 (it) | 1992-12-22 |
ITMI922927A1 (it) | 1994-06-22 |
FR2685807A1 (fr) | 1993-07-02 |
FR2685807B1 (fr) | 1995-11-03 |
GB2262850B (en) | 1996-04-17 |
IT1256217B (it) | 1995-11-29 |
GB9226862D0 (en) | 1993-02-17 |
KR940008206B1 (ko) | 1994-09-08 |
KR930014615A (ko) | 1993-07-23 |
JPH05259473A (ja) | 1993-10-08 |
JP2677747B2 (ja) | 1997-11-17 |
DE4242801A1 (zh) | 1993-07-01 |
DE4242801C2 (de) | 2000-02-10 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TW473786B (en) | Method and apparatus for reducing stress across capacitors used in integrated circuits | |
TW488060B (en) | Ferroelectric memory | |
TW295683B (zh) | ||
TW472445B (en) | Semiconductor integrated circuit | |
TW319837B (zh) | ||
TW389906B (en) | Mode setting circuit for memory devices | |
JPS60107857A (ja) | 集積回路チツプにおける電圧発生回路 | |
TW269760B (zh) | ||
TW558829B (en) | Reduced potential generation circuit operable at low power-supply potential | |
TW457600B (en) | Power supply adjusting circuit and a semiconductor device using the same | |
TW305045B (zh) | ||
TW307043B (en) | A semiconductor memory device with on-chip boosted power supply voltage generator | |
TW564338B (en) | Voltage regulator | |
TW209926B (zh) | ||
TW417283B (en) | Voltage level shifting circuit | |
TW422991B (en) | A power supply voltage boosting circuit in a semiconductor memory device | |
TW379329B (en) | Charge pump circuit and logic circuit | |
TW455755B (en) | Automatic clearing circuit | |
TW504887B (en) | Voltage booster circuit apparatus and control method therefor | |
TW384483B (en) | Integrated circuit semiconductor memory device incorporating internal power supply voltage generator | |
TW396604B (en) | Internal power supply voltage generating circuit and the method for controlling thereof | |
TW417280B (en) | A voltage generation circuit of a semiconductor memory device | |
CN108664067A (zh) | 具有高带宽和电源抑制的低泄漏低压差稳压器 | |
TW516031B (en) | Voltage boost level clamping circuit for a flash memory | |
US5986935A (en) | Semiconductor memory device with high voltage generation circuit |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
MM4A | Annulment or lapse of patent due to non-payment of fees |