GB2291296A - Switching circuit for EEPROM - Google Patents

Abstract

A high voltage switching circuit includes a buffer circuit 30 for buffering an input signal, a high voltage pumping circuit 40 for producing a desired voltage in response to an output signal of the buffer circuit 30, and a disconnecting circuit 50 for disconnecting the buffer circuit 30 and high voltage pumping circuit 40 when the output voltage of the buffer circuit 30 is a voltage Vcc and that of the high voltage pumping circuit 40 is a high voltage, wherein the disconnecting circuit 50 includes a transistor 34 and 36, a first channel region adjacent to a source of the transistor has a different conductivity type from a channel region adjacent to a drain of the transistor (fig. 4). Transistor 34 is an enhancement transistor and transistor 36 is a depletion transistor. <IMAGE>

Description

SWITCHING CIRCUIT The present invention relates to semiconductor memory devices, and more particularly to voltage switching circuits therefor.

For an EEPROM (Electrically Erasable Programmable Read Only Memory), a destructive voltage across a transistor is a serious problem caused by a high voltage produced in a memory integrated circuit when programming or erasing data.

A conventional high voltage switching circuit shown in Figure 1 of the accompanying diagrammatic drawings includes a NAND gate 10 for buffering input signals, a depletion type transistor 12 having a channel connected between an output terminal of NAND gate 10 and a first node 11 for disconnecting a source voltage from a high voltage, and a high voltage pumping circuit 14 connected between the first node 11 and an output terminal for producing either a high voltage or a ground voltage in response to the input signals.The high voltage pumping circuit 14 further includes a first NMOS transistor 16 having a channel connected between a high voltage supply Vpp and a second node 22 and further having a gate connected to the first node 11, a second NMOS transistor 18 having a channel connected between the first and second nodes 11 and 22 and further having a gate connected to the second node 22, and a third NMOS transistor 25 having a gate connected to the second node 22 and a channel having both terminals commonly connected to each other.

In a high voltage switching operation, the input terminal VN is supplied with a high voltage, a first input (')D of NAND gate 10 is maintained at a high state, a gate input (t)P of depletion transistor 12 is at a low state, and an input < D of the third NMOS transistor 25 makes periodic oscillations. In this case, if a second input of NAND gate 10 receives a signal having a high level, the output of NAND gate 10 is at a ground level and, therefore, so is first node 11.

However, if the second input of NAND gate 10 receives a signal having a low level, the output of NAND gate 10 is at high level. Depletion transistor 12 is turned on to provide the first node 11 with a voltage obtained by subtracting the threshold voltage of transistor 12 from the high level of NAND gate 10, thereby driving the high voltage pumping circuit 14. Also, depletion transistor 12 disconnects the output voltage of NAND gate 10 from the high voltage of first node 11. In this case, the gate of transistor 12 is provided with a ground voltage. If the gate of depletion transistor 12 is provided with a source voltage Vcc, a short circuit operation occurs between high voltage supply Vpp and source voltage Vcc,so as not to produce a high voltage on the output terminal.

In a high voltage switching operation, a breakdown voltage across depletion transistor 12 occurs due to an electric field between the gate and drain of depletion transistor 12 when the output terminal is raised to a high voltage and the gate of depletion transistor 12 is grounded. Hencc, a high voltage at the output terminal may not be produced above a given value, in order to prevent this problem. The problem can be resolved through the manufacturing process. However, the size of the semiconductor integrated circuit is unavoidably increased, making it difficult to achieve a highly integrated circuit.

Preferred embodiments of the present invention aim to provide a high voltage switching circuit for a semiconductor memory device that produces a desired high voltage.

According to one aspect of the present invention, a high voltage switching circuit for a semiconductor memory device includes a depletion type transistor and enhancement type transistor connected in series. Their gates are connected to a source voltage, whereby the intensity of the electric field across the gate and drain of the transistors is reduced, thereby raising the break-down voltage.

According to another aspect of the present invention, there is provided a high voltage switching circuit comprising: a buffer means for buffering an input signal; a high voltage pumping means for producing a given voltage in response to an output signal of said buffer means; and a disconnecting means connected between said buffer means and said high voltage pumping means, for disconnecting said buffer means and high voltage pumping circuit when said output voltage of said buffer means is a source voltage and the output signal of said high voltage pumping circuit is a high voltage, said disconnecting means comprising an enhancement transistor and depletion transistor connected in serics, gates of said enhancement transistor and said depletion transistor being commonly connected to said source voltage.

Preferably, said buffer means is an inverter, NAND gate or NOR gate.

Preferably, said enhancement and depletion transistors comprise adjacent channels formed below a common gate.

According to a further aspect of the present invention, there is provided a high voltage switching circuit comprising: a buffer means for buffering an input signal; a high voltage pumping circuit for producing a desired voltage in response to an output signal of said buffer means; and a disconnecting transistor means connected between said buffer means and said high voltage pumping circuit for disconnecting said buffer means and said high voltage pumping circuit when said output voltage of said buffer means is a source voltage and the output voltage of said high voltage pumping circuit is a high voltage, wherein a first channel region adjacent to a source of said disconnecting transistor means has a different conductive type from a channel region adjacent to a drain of said disconnecting transistor means.

Preferably, said disconnecting transistor means comprises a depletion transistor and an enhancement transistor, a channel of said depletion transistor being said first channel region, a channel of said enhancement transistor being said second channel region.

Preferably, a gate of said disconnecting transistor means is connected with said source voltage.

Preferably, said depletion transistor of said disconnecting transistor means is connected with an output terminal of said high voltage pumping circuit.

The invention extends to a semiconductor memory device provided with a high voltage switching circuit according to any of the preceding aspects of the invention.

For a better understanding of the invention and to show how the same may be carried into effect, reference will now be made, by way of example, to Figures 2 to 5 of the accompanying diagrammatic drawings, in which: Figure 2 is a schematic diagram of one example of a circuit according to an embodiment of the present invention; Figure 3 is a layout for producing the circuit of Figure 2; Figure 4 is a cross sectional view taken along line A-A' of Figure 3; and Figure 5 is a graph comparing breakdown voltages characteristic of enhancement and depletion transistors according to the circuit of Figure 2 with that of conventional circuits.

A high voltage switching circuit shown in Figure 2 includes an inverting circuit 30 for buffering an input control signal, a high voltage pumping circuit 40 for producing a high or ground voltage in response to output signals from inverting circuit 30 and a disconnecting circuit 50 for electrically disconnecting the inverting circuit 30 from high voltage pumping circuit 40. In this case, inverting circuit 30 may be substituted by a NAND gate or NOR gate. Disconnecting circuit 50 includes a depletion type transistor 36 and an enhancement type transistor 34.

In high voltage switching operation, an input terminal Vpp is provided with a high voltage, and input CI) makes periodic oscillations. If the control input of inverting circuit 30 is high, first, second and third nodes 31, 32 and 33 become low, so that high voltage pumping circuit 40 is not driven.

However, if the control input of inverting circuit 30 is low, the first node 31 becomes high, and the second node 32 is dropped from a source voltage Vcc to a voltage VCC~V,E that is obtained by subtracting a threshold voltage Vm of enhancement transistor 34 from source voltage Vcc. The voltage VCC~V1E drives high voltage pumping circuit 40 to raise the voltage level of output terminal, i.e. third node 33 is raised to high voltage Vpp. The third node 33 and voltage source node 31 are electrically disconnected by enhancement mode transistor 34.

Referring to Figure 3, a device region 60, a polysilicon layer 62 for a gate extending in a given direction over device region 60, and a depletion ion implantation region 64 overlapping a portion of polvsilicon layer 62 in device region 60 are formed in a semiconductor substrate.

Device region 60 shown in Figure 4 is limited by a field oxide layer 70, and includes a source 66 and a drain 68 separated from each other by a channel region, and gate 62 of polysilicon formed over the channel region.

Depletion mode transistor 36 and enhancement mode transistor 34 are formed in the channel region.

With reference to Figure 5, the breakdown voltage characteristics of enhancement and depletion transistors according to the circuit of Figure 2 are compared with those of conventional circuits. Vertical and horizontal axes represent the current and voltage respectively between a drain and source. A line indicated by reference numeral 71 represents a characteristic curve of enhancement NMOS transistor 34 having the gate and source connected to a ground voltage. A line indicated by reference numeral 73 represents a characteristic curve of a floating-source enhancement NMOS transistor having a gate connected to the source voltage according to prior art. The line indicated by reference numeral 75 represents a characteristic curve of a depletion NMOS transistor having a gate connected to a ground voltage and a source to the source voltage according to prior art.The line indicated by reference numeral 77 represents a characteristic curve of floating-source depletion transistor 36 having its gate connected to source voltage. Thus, it may be seen apparent that the highest transistor breakdown voltage is obtained by the circuit of Figure 2.

As stated above, the illustrated switching circuit employs a disconnecting circuit for disconnecting the high voltage of the output terminal and the output voltage of the buffer circuit. The switching circuit includes enhancement and depletion transistors having channels connected in series and gates commonly provided with the source voltage. Thus, electric fields applied to the gate and drain of the transistors are lessened when the output voltage is raised to a high level. As a result, the break-down voltage of the transistors is increased so as to produce the desired high voltage at the output terminal of the circuit.

Furthermore, since enhancement and depletion transistors are simultaneously formed in one channel, the layout area of the integrated circuit may be reduced, to achieve a semiconductor memory device having high density. Consequently, a high voltage switching circuit having a maximum high voltage in a minimum size integrated circuit is obtained.

While a preferred embodiment of the invention has been shown and described in detail, it will be apparent to those skilled in the art that modifications in detail may be made without departing from the spirit and scope of the invention.

The term "ground potential" (or like terms such as "ground voltage" or "earth" potential or voltage) is used conveniently in this specification to denote a reference potential. As will be understood by those skilled in the art, although such reference potential may typically be zero potential, it is not essential that it is so, and may be a reference potential other than zero.

The reader's attention is directed to all papers and documents which are filed concurrently with or previous to this specification in connection with this application and which are open to public inspection with this specification, and the contents of all such papers and documents are incorporated herein by reference.

All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and/or all of the steps of any method or process so disclosed, may be combined in any combination, except combinations where at least some of such features and/or steps are mutually exclusive.

Each feature disclosed in this specification (including any accompanying claims, abstract and drawings), may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise.

Thus, unless expressly stated otherwise, each feature disclosed is one example only of a generic series of equivalent or similar features.

The invention is not restricted to the details of the foregoing embodiment(s). The invention extends to any novel one, or any novel combination, of the features disclosed in this specification (including any accompanying claims, abstract and drawings), or to any novel one, or any novel combination, of the steps of any method or process so disclosed.

Claims (6)

CLAIMS:

1. A high voltage switching circuit comprising: a buffer means for buffering an input signal; a high voltage pumping circuit for producing a desired voltage in response to an output signal of said buffer means; and a disconnecting transistor means connected between said buffer means and said high voltage pumping circuit for disconnecting said buffer means and said high voltage pumping circuit when said output voltage of said buffer means is a source voltage and the output voltage of said high voltage pumping circuit is a high voltage, wherein a first channel region adjacent to a source of said disconnecting transistor means has a different conductive type from a channel region adjacent to a drain of said disconnecting transistor means.

2. A high voltage switching circuit according to claim 1, wherein said disconnecting transistor means comprises a depletion transistor and an enhancement transistor, a channel of said depletion transistor being said first channel region, a channel of said enhancement transistor being said second channel region.

3. A high voltage switching circuit according to claim 2, wherein said depletion transistor of said disconnecting transistor means is connected with an output terminal of said high voltage pumping circuit.

4. A high voltage switching circuit according to any one of claims 1-3, wherein a gate of said disconnecting transistor means is connected with said source voltage.

5. A high voltage switching circuit substantially as hereinbefore described with reference to Figures 2 to 6 of the accompanying drawings.

6. A semiconductor memory device provided with a high voltage switching circuit according to any of the preceding claims.