IT1255121B - Matrice di memoria non volatile con protezione da sovra- cancellazione - Google Patents

Matrice di memoria non volatile con protezione da sovra- cancellazione

Info

Publication number
IT1255121B
IT1255121B ITMI921050A ITMI921050A IT1255121B IT 1255121 B IT1255121 B IT 1255121B IT MI921050 A ITMI921050 A IT MI921050A IT MI921050 A ITMI921050 A IT MI921050A IT 1255121 B IT1255121 B IT 1255121B
Authority
IT
Italy
Prior art keywords
memory matrix
row
flash
over
flash cell
Prior art date
Application number
ITMI921050A
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of ITMI921050A0 publication Critical patent/ITMI921050A0/it
Publication of ITMI921050A1 publication Critical patent/ITMI921050A1/it
Application granted granted Critical
Publication of IT1255121B publication Critical patent/IT1255121B/it

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/30—Power supply circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories

Landscapes

  • Read Only Memory (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

Una matrice di memoria formata da celle veloci (flash) a transistor singolo impiega circuiteria di prevenzione per minimizzare l'effetto di qualsiasi porta fluttuante in uno stato sovra-cancellato nell'accedere a dati memorizzati nel dispositivo a matrice di memoria. Il circuito di prevenzione include una linea di colonna collegante un dispositivo limitatore di corrente in ciascuna riga assieme in una colonna comune. Il dispositivo a matrice di memoria impiega pure un dispositivo limitatore di corrente di riga che collega tale riga di celle flash al potenziale di cancellazione. I secondi mezzi di commutazione di riga sono attivati per impedire che un falso segnale generato da una cella flash sovracancellata nella medesima colonna di una cella flash selezionata a cui viene fatto accesso relativamente a dati abbia a mascherare il recupero di dati dalla cella flash desiderata.
ITMI921050A 1991-05-03 1992-04-30 Matrice di memoria non volatile con protezione da sovra- cancellazione IT1255121B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/695,481 US5241507A (en) 1991-05-03 1991-05-03 One transistor cell flash memory assay with over-erase protection

Publications (3)

Publication Number Publication Date
ITMI921050A0 ITMI921050A0 (it) 1992-04-30
ITMI921050A1 ITMI921050A1 (it) 1993-10-30
IT1255121B true IT1255121B (it) 1995-10-20

Family

ID=24793164

Family Applications (1)

Application Number Title Priority Date Filing Date
ITMI921050A IT1255121B (it) 1991-05-03 1992-04-30 Matrice di memoria non volatile con protezione da sovra- cancellazione

Country Status (5)

Country Link
US (1) US5241507A (it)
JP (1) JP3195045B2 (it)
KR (1) KR100241993B1 (it)
DE (1) DE4213741C2 (it)
IT (1) IT1255121B (it)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2870260B2 (ja) * 1991-09-27 1999-03-17 日本電気株式会社 不揮発性半導体記憶装置
US5388069A (en) * 1992-03-19 1995-02-07 Fujitsu Limited Nonvolatile semiconductor memory device for preventing erroneous operation caused by over-erase phenomenon
US5420822A (en) * 1992-03-31 1995-05-30 Kabushiki Kaisha Toshiba Non-volatile semiconductor memory device
JPH0644791A (ja) * 1992-05-08 1994-02-18 Seiko Epson Corp 不揮発性半導体装置
JP3348466B2 (ja) * 1992-06-09 2002-11-20 セイコーエプソン株式会社 不揮発性半導体装置
US5398204A (en) * 1992-11-09 1995-03-14 Seiko Epson Corporation Nonvolatile semiconductor system
US5452251A (en) 1992-12-03 1995-09-19 Fujitsu Limited Semiconductor memory device for selecting and deselecting blocks of word lines
US5324998A (en) * 1993-02-10 1994-06-28 Micron Semiconductor, Inc. Zero power reprogrammable flash cell for a programmable logic device
DE69325443T2 (de) * 1993-03-18 2000-01-27 Stmicroelectronics S.R.L., Agrate Brianza Verfahren zur Vorspannung einer nichtflüchtigen Flash-EEPROM-Speicheranordnung
US5359558A (en) * 1993-08-23 1994-10-25 Advanced Micro Devices, Inc. Flash eeprom array with improved high endurance
US5479368A (en) * 1993-09-30 1995-12-26 Cirrus Logic, Inc. Spacer flash cell device with vertically oriented floating gate
US5640031A (en) * 1993-09-30 1997-06-17 Keshtbod; Parviz Spacer flash cell process
US5506816A (en) * 1994-09-06 1996-04-09 Nvx Corporation Memory cell array having compact word line arrangement
US5625600A (en) * 1995-05-05 1997-04-29 United Microelectronics Corporation Flash memory array with self-limiting erase
US5546340A (en) * 1995-06-13 1996-08-13 Advanced Micro Devices, Inc. Non-volatile memory array with over-erase correction
KR19980052496A (ko) * 1996-12-24 1998-09-25 김영환 플래쉬 메모리셀의 과소거 된 셀 확인 방법
US6614695B2 (en) 2001-08-24 2003-09-02 Micron Technology, Inc. Non-volatile memory with block erase
US7692973B2 (en) * 2006-03-31 2010-04-06 Semiconductor Energy Laboratory Co., Ltd Semiconductor device
JP5238178B2 (ja) * 2006-03-31 2013-07-17 株式会社半導体エネルギー研究所 半導体装置
US8059458B2 (en) * 2007-12-31 2011-11-15 Cypress Semiconductor Corporation 3T high density nvDRAM cell
US8064255B2 (en) 2007-12-31 2011-11-22 Cypress Semiconductor Corporation Architecture of a nvDRAM array and its sense regime

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3693174A (en) * 1971-07-06 1972-09-19 Litton Systems Inc Associative memory device and system
US3750115A (en) * 1972-04-28 1973-07-31 Gen Electric Read mostly associative memory cell for universal logic
US3800297A (en) * 1972-06-03 1974-03-26 Gen Electric Non-volatile associative memory
GB1494833A (en) * 1974-10-11 1977-12-14 Plessey Co Ltd Content addressable memories
US4387447A (en) * 1980-02-04 1983-06-07 Texas Instruments Incorporated Column and ground select sequence in electrically programmable memory
JPH0760864B2 (ja) * 1984-07-13 1995-06-28 株式会社日立製作所 半導体集積回路装置
JPS61145636A (ja) * 1984-12-19 1986-07-03 Nec Corp 記号列照合装置
KR950008676B1 (ko) * 1986-04-23 1995-08-04 가부시기가이샤 히다찌세이사꾸쇼 반도체 메모리 장치 및 그의 결함 구제 방법
JPS62266793A (ja) * 1986-05-13 1987-11-19 Mitsubishi Electric Corp 不揮発性半導体記憶装置
US4783766A (en) * 1986-05-30 1988-11-08 Seeq Technology, Inc. Block electrically erasable EEPROM
US4937790A (en) * 1987-08-31 1990-06-26 Hitachi, Ltd. Semiconductor memory device
US4888735A (en) * 1987-12-30 1989-12-19 Elite Semiconductor & Systems Int'l., Inc. ROM cell and array configuration
US4888738A (en) * 1988-06-29 1989-12-19 Seeq Technology Current-regulated, voltage-regulated erase circuit for EEPROM memory
JP2685825B2 (ja) * 1988-08-12 1997-12-03 株式会社東芝 不揮発性半導体メモリ
US4999812A (en) * 1988-11-23 1991-03-12 National Semiconductor Corp. Architecture for a flash erase EEPROM memory
US5097444A (en) * 1989-11-29 1992-03-17 Rohm Corporation Tunnel EEPROM with overerase protection
US5122985A (en) * 1990-04-16 1992-06-16 Giovani Santin Circuit and method for erasing eeprom memory arrays to prevent over-erased cells

Also Published As

Publication number Publication date
KR920022304A (ko) 1992-12-19
DE4213741A1 (de) 1992-11-19
JPH05159589A (ja) 1993-06-25
ITMI921050A1 (it) 1993-10-30
US5241507A (en) 1993-08-31
ITMI921050A0 (it) 1992-04-30
DE4213741C2 (de) 2002-10-31
KR100241993B1 (ko) 2000-03-02
JP3195045B2 (ja) 2001-08-06

Similar Documents

Publication Publication Date Title
IT1255121B (it) Matrice di memoria non volatile con protezione da sovra- cancellazione
JP3091687B2 (ja) センス増幅回路
US20010015913A1 (en) Non-volatile semiconductor memory device and data programming method
US20040076037A1 (en) Flash memory architecture with page mode erase using NMOS and PMOS row decoding scheme
US5574686A (en) Nonvolatile semiconductor storage system
KR960018639A (ko) 온 상태 결함의 가능성을 줄인 공간 광 변조기
KR940006141A (ko) 불휘발성 반도체 메모리시스템
KR20020002286A (ko) 반도체집적회로
US5406516A (en) Semiconductor memory device
US7391648B2 (en) Low voltage sense amplifier for operation under a reduced bit line bias voltage
JP2006338855A (ja) 消去動作時ビットライン電圧を放電するページバッファを具備したｎａｎｄフラッシュメモリ装置
KR100300696B1 (ko) 반도체기억장치
JP2638654B2 (ja) 半導体不揮発性記憶装置
KR920006983A (ko) 저잡음 감지 구조를 가진 반도체 메모리 장치
JPS5922295A (ja) 半導体記憶装置
US7280400B2 (en) Reducing sneak currents in virtual ground memory arrays
US5995414A (en) Non-volatile semiconductor memory device
US4004286A (en) Programmable random access memory (PRAM) integrated circuit memory device
JPH01134793A (ja) 不揮発性半導体記憶装置
JPH04351794A (ja) 不揮発性記憶装置
ITMI911485A1 (it) Circuito di precarica di bit line per la lettura di una cella di memoria eprom.
US8891310B2 (en) EEPROM memory protected against breakdown of control gate transistors
EP0317984A2 (en) Nonvolatile memory
TWI270076B (en) Flash memory cell array structure featuring selectable bit data modification
JP3011415B2 (ja) 不揮発性半導体メモリ装置

Legal Events

Date Code Title Description
0001 Granted
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19970423