TWI270076B - Flash memory cell array structure featuring selectable bit data modification - Google Patents

Abstract

The present invention relates to a flash memory cell array structure, in which each memory cell includes a split-gate memory cell and a selected transistor. A source/drain of the selected transistor is serially connected with the source of the split-gate memory cell; the other source/drain of the selected transistor is connected with the selected transistor of another memory cell. In other words, two neighboring rows are mirror-symmetrical, and each word line are connected with the respective control gate of each row of flash memory cells; moreover, each transmission gate lines are also connected with the respective gate of all selected transistors; each source line is connected with the connection terminals of all two neighboring selected transistors of eight neighboring bit lines. Besides, each bit line is connected with the drain of each split-gate memory cell respectively on the same row. The structure of the present invention won't interfere with the memory cells of neighboring columns while programming a column of memory cells, and the memory cell of each byte associated with each cell on the same column can be either individually erased by data or not be erased.

Description

1270076

V. INSTRUCTIONS OF THE INVENTION (1) Field of the Invention: The invention is directed to a gate-separated flash memory 70 in a semiconductor integrated circuit', particularly a flash memory cell array structure in which a selectable bit data is modified. Background of the invention: Mobility system, record (external, after the capital is saved, other comparable, potential. No action power, 0, high stability information can be eliminated or eliminated). Can retain the storage and storage flash memory is only a digital phone and other electronic systems, such as a kind of security is more effective than the flash system, the system has a camera, product, and full data rate. Memory words, in order to at least the eclipse of the notebook type, after flashing, memory access memory block tuple, the current decade, so competitive computer, memory speed, and defense The new block (blocks) sequence record is so slow that no longer need any technology even on the power supply. This advantage and other storage. The demand for handheld electronic records in the future is slower than that of shock and resistance. This power source is in the middle of the media has become a messy thing, the secret can not flash quickly recall the poor storage of the cell, with a flash memory cell 10 as an example 'Please refer to the figure - Figure' contains ^ Control interpole 12, - floating gap 18, a source 16, a drain 14, a coupling oxide layer 15 and an FN tunneling

I27〇〇76, invention description (2), ^^ layer 1 3, / cryptic cells are usually formatted before use. This is the result of dividing the data f. At this time, the control gate 12 is connected to a positive voltage, for example, 3 volts 'source 1 6 ground, drain 1 4 grounded, if the floating gate 1 8 has electron storage: ' then the FN tunneling oxide layer 1 3 to control gate 1 2 (path L 2 ). And / month removes the floating gate 1 8 electrons. To change the state of the memory cell, it must be stylized. Stylized

, 'Source 1 16 is connected to a positive voltage, such as 1 〇V. The control gate 丨2 is connected to a small voltage such as 1 Q • 8 volts. The drain is 1 4 grounded or very low voltage. As long as the coupling oxidation = 15 = thin, the deuterium hot electrons 11 will not follow the path) L1, to the source 16 but the teeth change with the coupling oxide layer 15 to the floating gate 18 (path L1) The state of the floating gate. Referring to the second figure, this figure shows a typical flash memory cell array. 1. Each of the two adjacent columns of memory cells in the flash memory cell array structure is a common source. For example, an odd column memory cell unit 201 and a plurality of even numbers 歹J. The cell unit 2 〇 2 has a common source 2 6 and has a common source line SL as an axis of symmetry. And f mirror symmetry. Bit line BL connects all memories of the same row (c〇lumn) = single bungee. Each word line WL is connected to the same column of memory cells. In general, the flash memory cell array structure described above may cause some unavoidable situations when the data is erased. ^ When data is erased from the flash memory cell array, the whole column is used as the data wipe: 1270076 V. The unit of invention description (3). Because once a WL force σ is used to erase the positive voltage, the corresponding common source line is grounded, so all the memory cell data connected to the entire selected word line is erased. It is not possible to use a byte as an erase unit. This is very inconvenient for some non-volatile memory cards because it is not possible to remove only a specified memory cell content. In addition, in conventional flash memory cell arrays, if two adjacent flash memory cells of the shared source are not programmed at the same time, the flash memory that is not programmed will be interfered. The reason is as follows: for example, a column of memory cells 2 1 is to be programmed, and a memory cell of an adjacent column is not. At this time, the word line WL1 provides a control gate voltage of 1.8V, WL2 is grounded, and the common source line SL is added with 1 3V. At this time, the data is input by 8 bit lines BL (one bit has 8 bits) Meta-line) to write data in units of bytes. However, even if WL2 is grounded, it is difficult to ensure that the stored data will be disturbed by the high voltage on the common source line, and the number of stored electrons on the floating gate will be reduced. Therefore, the information is unstable or incomplete. In view of this, the practitioners engaged in the design and development of flash memory system technology are not committed to researching the structure of the improved flash memory cell array, and can not save the selected location tuple stored in the data erasure. Data; and the problem of gradual destruction of data stored by other bytes when stylizing the selected location tuple. Summary of the invention:

Page 6 1270076 V. INSTRUCTIONS (4) The main object of the present invention is to provide a flash memory cell array structure in which a selected byte is programmed, and there is a presence between adjacent bytes. The isolation zone' avoids the risk of damage to the poor material. A secondary object of the present invention is to provide a flash memory cell array structure, so that when data erasure is performed, it can be erased in units of bytes, without the need to Erase. The invention discloses a flash memory cell array structure, each memory cell unit comprises a gate memory cell and a selective transistor, and one source/drain of the selective transistor and a source frequency of the channel memory cell Then, the other source/drain of the selective transistor is connected to the selective transistor of another memory cell. In other words, the adjacent two columns are mirror-symmetrical; the word lines are respectively connected to the control gates of each column of flash memory cells; in addition, each of the transfer gate lines is also connected to the gates of all the selective transistors of the same column. . The source line is connected to the connection ends of all of the two adjacent selective transistors of the eight adjacent 8-bit lines. In addition, each bit line is connected to the drain of each of the same memory cells. This structure allows a column of memory cells to be programmed without interfering with the memory cells of adjacent columns. And the memory cells of each tuple of each memory cell in the same column can be erased or not erased by the data alone. Detailed description of the invention:

Page 7 1270076 V. Description of the invention (5) In view of the fact that the typical flash memory cell array is programmed for the selected byte, it will destroy the data stored by other bytes and the single wipe that cannot be effectively used. In addition to or retaining the data stored by the selected positioning tuple, the present invention provides a flash memory cell array structure to solve the above problems. Hereinafter, a detailed description of the present invention will be described. An embodiment of the present invention provides a flash memory cell array structure formed on a semiconductor substrate. Please refer to the third figure, which is composed of a complex array of odd-numbered columns 3 〇 1 memory cells, and a complex array of even-numbered columns 3 0 2 memory cells. The memory cell unit (for example, 3 0 1 ) comprises a selective transistor (se 1 ectedtransist 〇r ) 3 0 4 and a gate flash flash memory cell 3 0 3 . This array structure differs from the conventional opening flash memory cell array in that the two common sources are separated by flash memory cells 3 0 3 and 3 0 5 by two selective transistors (3616 <^6(148113131;〇] :) 30 4 and 30 6 are separated, all voltages applied to the open flash memory cell source 3 6 need to be turned on to the source through the selective transistors 3 〇 4 and 3 0 6 ' When a shutter flash memory cell, for example, 3 0 3 is being programmed, the selective transistor 300 is turned on, and the adjacent selective flash transistor 3 is turned off by the selective transistor 3 〇6 is blocked (so selective transistor 306 is high impedance), so it will not be disturbed. In addition, another advantage of the above-mentioned opening flash memory cell array structure is that all memory cells in the same column It is also possible to erase data in units of one tuple. Unlike traditional flash memory cells, only one column of data can be used.

1270076 V. Description of invention (6) The unit erases the data. Further explanation is as follows: Please refer to the fourth figure. The flash memory cell array structure of the fourth figure is exemplified by an array of m X η bytes. Where m represents m columns of memory cells and η represents n bytes. Therefore, according to the above flash memory cell array, at least (1) η X 8 bit lines are recorded in BLk, and k is from 0 to 7. (2) m word lines are denoted as WL WL2..., WL(m-1), WLm, respectively. Each word line is connected to the control gate of the flash memory cell of each column of memory cells. (3) m transmission gate lines are denoted as G L 1 , G L 2..., GL(m-l ), GLm, respectively. To connect the gates of the selective transistors of each column, wherein if the kth pass gate line is adjacent to the k+1 pass gate line, the k + 2 pass gate lines are separated by the k+ The word line and the k + 2 word line, where m-l>k> = :i. (4) η source lines, each source line connecting the 汲 extremes of all selective transistors of adjacent octets (B L 1 , B L 2, ..., B L 7 ) of the same byte. Therefore, to program any of the above bytes, for example, to program the (i, j) byte as an example. Referring to FIG. 5, at this time, the source line SL j applies a source voltage of about 10 V; a turn-on voltage of about 1 1 V is applied to the gate line GL i to make the source voltage of the 10 V pass-through gate. The source of the pole flashing flash memory cell 4, the gate line other than GL i GLk force 0 V voltage, where k# i, will make the same row, the different columns of selective transistor non-conducting, Prevent all data in the flash memory of k-cut i from being disturbed. The word line WL i applies a control gate voltage of about 1.8 V. Therefore, when a tuple data "logic 0" (example 1270076 V, invention description (7) such as 0 V or 0.5 V) or logic 1 (for example 5 V) is presented in the (i, j) byte memory When the bit line of the cell unit (BL0, BL1..... BL7), the data of BL0 will be written in the (i, j) byte memory cell unit (i, j 0 ) The flash memory cell 4 0 3 is in the floating gate 48. At the same time, the data of BL1 will be written in the (i,j) byte memory cell unit (i, j 1 ) to open the flash memory cell 4 In the floating gate 4 8 ' of 0 3, as shown in the figure, other bit lines BL k, k = 2 to 7 also write data into the corresponding memory cells. The above "write" means Changing the logic state of the floating gate, when the voltage on the bit line is logic 1 (for example, 5 V), will not change the logic state of the floating gate, and the voltage on the bit line is logic 0 (for example, 0 V or 0). When 5 V ), the electrons are stored in the floating gate to make it assume a logic 1 state. Among them, the selective transistor 410, because GL (i + 1) plus 0 volts, is not conductive. In other words, the data in the floating gate of the flash memory cell 4 is not affected, even if the source voltage is large. The marching unit cell note \) / column y X, the first C, for example, the order of the group of one yuan is a certain pair, the step is to add a line of the material and the group is added to the line The selection of the crystal body of the pole gate is selected and tested. Source change, non-line material level: group, lower element line, such as bit word pressure, his cell's cell memory, flash gate block diagram, application of gate voltage WLx about 1 3V control gate voltage; all bits The line is floating; a turn-on voltage of about 7 V is applied to the gate line GLX;

Page 10 1270076 V. Description of the invention (8) Apply a source voltage of 0V (ground) to the source line SLy; apply a source of about 6 V to the source line SL w (w = 1~η, and w# y ) a pole voltage; wherein, GLx is turned on so that all of the selective transistors 5 0 5 , 6 0 5 of the Xth column are turned on, so that the source voltage (ground signal) is selected by the selective transistors 5 0 5, 6 0 5 Passed to the source 5 6 , 6 6 . At this time, except for the source line S 1 y being 0 volts, the electrons in the floating gate of the (X, y)th byte flash memory cell 6 0 5 are removed, and the rest of the SL w (w = 1~η, and w off y) due to the application of a source voltage of about 6 V, so that in addition to the (X, y) byte, the other blocking flash memory cells in the same column will be 5 0 5 The control gate voltage is insufficient to attract the electrons of the floating gate and the data is retained. It can be seen from the above that the embodiment of the present invention is a flash memory cell array structure formed by connecting a memory cell and a selective transistor in series to form a memory cell unit. The array structure has the following advantages: 1. When stylizing the selected positioning tuple, it can be isolated and protected from other unselected bytes to avoid damaging the data stored by the byte; and 2. when erasing the word line The data stored in the selected positioning tuple can be retained. The above description is based on the preferred embodiment of the present invention. The voltage values applied to the source line, the bit line, the word line, and the gate line in the embodiment may be based on the actual flash memory cell array structure. Design needs to be

Page 11 1270076

Page 12 1270076 BRIEF DESCRIPTION OF THE DRAWINGS The first figure is a schematic diagram of the structure of a conventional flash memory cell; the second figure is a schematic circuit diagram of a typical flash memory cell array structure; the third figure is an embodiment of the present invention. The circuit of the flash memory cell array structure is not intended, and the fourth figure is a circuit diagram of another flash memory cell array structure according to an embodiment of the present invention; the fifth figure is a programmatically selected bit group according to an embodiment of the present invention. The figure is a schematic diagram of the data stored in the selected positioning tuple when the data is erased in the embodiment of the present invention. Description of the figure: Memory cell-1 0, 2 0 1 , 2 0 2, 3 0 1 , 3 0 2 Hot electron -1 1 Control gate -1 2, 3 2, 5 2, 6 2 Bungee-14 , 34, 340, 34 342, 44, 44' gate oxide layer-1 5 ❿ source-16, 26, 36, 46, 46', 462, 56, 66 floating gate -18, 48, 48 , 58, 68 bytes - (i + l, j), (i, j), (x, l), (x, yl), (x, y), (x, y + 1), (x , n) opening memory cell - 3 0 3, 3 0 5, 4 0 3 selective transistor - 3 0 4, 3 0 6, 4 0 5, 4 0 6 , 5 0 5, 6 0 5

Page 13 1270076

Brief description of the pattern Transistor gate - 3 2 0 hot electron path -LI, LI', L2 source line - S L bit line - B L word line - WL gate line - G L Page 14 <1

Claims (1)

1270076 6. Patent application scope 1. A flash memory cell formed on a semiconductor substrate, comprising at least: a gate memory cell and a selective transistor are connected in series to a source of the gate memory cell, when When the selective transistor is turned on, the voltage applied by the drain of the selective transistor is transmitted to the source, so that the flash memory cell unit is programmed and erased. 2. The flash memory cell unit of claim 1, wherein the stylizing system turns on the selective transistor such that a source positive voltage is transmitted to the gate memory via the selective transistor. a source of the cell, and the control gate of the gate memory cell has a control gate positive voltage, the source positive voltage being greater than the control gate positive voltage, by applying a threshold voltage to the gate memory cell The logic state determines whether the flash memory cell is programmed. 3. The flash memory cell unit of claim 1, wherein the data erasing operation is to turn on the selective transistor to transmit a ground reference potential connected to one end of the selective transistor to the The source of the memory cell is opened, and the control gate of the opening memory cell applies a data erase positive voltage to remove electrons in the floating gate of the memory cell. 4. A flash memory cell array structure of (m X η ) bytes formed on a semiconductor substrate, comprising at least: m columns, η X 8 rows of memory cells arranged in an array structure, wherein Page 15 1270076 6. Patent Description Each memory cell includes a gate memory cell and a selective transistor, and the selective transistor is connected in series with the source of the channel memory cell; η X 8 a bit line for respectively connecting the drain of each of the same row of memory cells; m word lines for respectively connecting the control gates of each column of flash memory cells; m strips of gate lines for respectively connecting The gate of the selective transistor of each column, wherein the kth transfer gate line is adjacent to the k+1th pass gate line, and is separated from the k+2 pass gate line by the k+th word Line and k + 2 word lines, where m - 1 > k > = 1 ; and n source lines, each source line connecting all the selectivity of adjacent 8-bit lines of the same byte The extremes of the transistor. 5. The flash memory cell array structure of claim 4, wherein the above memory cell group can be programmed in a one-tuple unit. 6. The flash memory cell array structure of claim 5, wherein the programming of the selected (i, j)-byte memory cell unit comprises at least the following steps: The gate line is biased to turn on the voltage so that the selective transistor of the i-th column is turned on, and the selective transistor outside the i-th column is turned off to avoid interference of the data stored in the open flash memory cell other than the i-th column. ; add a control gate positive voltage to the control gate line of the i-th column, so that the i-th column is opened Page 16 1270076 Sixth, apply for the patent range flash memory; add a source positive voltage to the jth source line, the source positive voltage is greater than the positive voltage of the control gate, therefore, the memory cell of the j-bit group, All the memory cells of the j-byte are respectively written according to the state of the 8 bit lines of the j-byte. 7. The flash memory cell array structure according to claim 4, wherein the memory cell group can be erased in units of one tuple. 8. The flash memory cell array structure according to claim 7, wherein the data erasing of a selected (i, j) byte memory cell unit comprises at least the following steps: Passing the gate line plus the turn-on voltage, so that the i-th column selective transistor is turned on, and the selective transistor outside the i-th column is turned off; the positive voltage is erased from the i-th column word line to make the first The i-row opening flash memory is in the preparation state of data erasing; for the first, j-bit line is grounded, the bit line of k妾j is connected with a positive voltage for prohibiting erasing, and therefore, the memory cell of the j-bit group The transfer gate of the cell transmits ground to all of the open flash memory cell sources of the j-bit group for data erasure, and the data of the k-th byte is prevented from being erased. Page 17