TWI694449B - Memory system and method of operating memory - Google Patents

Abstract

The present disclosure provides a memory system and a method of operating memory. The memory system includes a flash memory chip and a controller. The controller is coupled with the flash memory chip, which the controller is configured to: receive a data with a first version from a file system in order to store the data corresponding to the first version in a first page of the flash memory chip; and program the data corresponding to a second version in the first page in response to the second version of the data, which the second version is newer than the first version.

Description

Memory system and memory operation method

The present disclosure relates to a memory and its operating method, and particularly to a memory system and a method of operating the memory.

Based on the characteristics of the flash memory hardware, strict management is required for the number of data writes and erases. On the one hand, when reading and writing frequently in the flash memory, the service life of electronic components is often reduced. On the other hand, in order to improve the data density of flash memory, a multi-level cell (multi-level cell) architecture has also been proposed, so that a memory cell can store multiple bits. In the multi-level unit architecture, although the amount of storable data can be increased to reduce the hardware cost, this architecture has relatively increased the requirements for error correcting codes.

In view of this, based on the electronic characteristics of flash memory, how to effectively overcome the requirements of reduced service life and reduced error correction is an urgent problem to be solved.

One aspect of this case is to provide a memory system including a flash memory chip and a controller. The controller is coupled to the flash memory chip, wherein the controller is configured to receive a data of a first version from a file system to store the data of the first version to a first of the flash memory chip A page; and in response to a second version of the data to program the second version of the data on the first page, wherein the second version is newer than the first version.

One aspect of this case is to provide a memory operation method. The memory operation method includes the following steps: receiving data of a first version from a file system to store the data of the first version to a first page of a flash memory chip through a controller; and responding A second version of the data, the second version of the data is programmed on the first page by the controller, wherein the second version is newer than the first version.

100‧‧‧Memory system

110‧‧‧Controller

120‧‧‧File System

130‧‧‧Flash memory conversion layer

131‧‧‧ Write data frequency analyzer

133‧‧‧Memory Recycler

135‧‧‧ interference processor

140‧‧‧Memory technology device layer

141‧‧‧program

143‧‧‧Reading program

145‧‧‧Erase procedure

150‧‧‧Flash memory chip

151‧‧‧General block range

153‧‧‧ rewritable block range

200‧‧‧ block

210, 220, 230‧‧‧ page

RW0, RW1, RW2, RW3, RW4

WL0, WL1, WL2 ‧‧‧ character line

A1~A4, B1~B4, C1‧‧‧ data

Vt‧‧‧critical voltage

Vp01, Vp02, Vp03, Vp04 ‧‧‧ voltage

Vp11‧‧‧Voltage

Vp21‧‧‧Voltage

Vr1~Vr4‧‧‧Read voltage

S410~S440, S510~S540, S610~S660

In order to make the above and other purposes, features, advantages and embodiments of the present case more obvious and understandable, the drawings are described as follows: Figure 1 is a schematic diagram of the architecture of a memory system according to some embodiments of the present case .

FIG. 2 is a schematic diagram of rewriting data to a block in the flash memory chip according to the flash memory system shown in FIG.

Figure 3A is shown in the programming resources according to some embodiments of the case A schematic diagram of the threshold voltage and the number of memory cells of the page in the block in FIG. 2 is expected.

FIG. 3B is a schematic diagram showing the threshold voltage and the number of memory cells of the pages in the programming data to the block in FIG. 2 according to some embodiments of the present case.

FIG. 3C is a schematic diagram showing the critical voltage and the number of memory cells of the pages in the programming data to the block in FIG. 2 according to some embodiments of the present case.

FIG. 4 is a flowchart of steps of a rewriting method according to some embodiments of the present case.

FIG. 5 is a flowchart of steps for performing memory recovery according to some embodiments of the present case.

FIG. 6 is a flowchart showing the steps of programming interference detection according to some embodiments of the present case.

The following disclosure provides many different embodiments or illustrations to implement the different features of this case. The elements and configurations in the specific illustrations are used to simplify this disclosure in the following discussion. Any illustrations discussed are for illustrative purposes only and do not limit the scope and significance of the case or its illustrations in any way. In addition, the present disclosure may repeatedly refer to numerical symbols and/or letters in different illustrations. These repetitions are for simplicity and explanation, and do not specify the relationship between different embodiments and/or configurations in the following discussion.

Used in the entire specification and patent application scope Terms (terms), unless otherwise noted, usually have the usual meaning that each word is used in this field, in the content disclosed here, and in special content. Certain terms used to describe this disclosure will be discussed elsewhere in this specification to provide additional guidance to those skilled in the art in the description of this disclosure.

With regard to "coupling" or "connection" used in this article, it can mean that two or more components directly make physical or electrical contact with each other, or indirectly make physical or electrical contact with each other, while "coupled" or "connected" "Connected" may also refer to the interoperation or movement of two or more elements.

In this document, the terms first, second, third, etc. are used to describe various elements, components, regions, layers, and/or blocks that can be understood. But these elements, components, regions, layers and/or blocks should not be limited by these terms. These words are only used to identify a single element, component, region, layer and/or block. Therefore, the first element, component, region, layer, and/or block in the following may also be referred to as the second element, component, region, layer, and/or block, without departing from the original intention of this case.

It is worth mentioning that, in this disclosure, the terms "save", "write" and "program" are used interchangeably, and the meaning should be understood as the same meaning without ambiguity.

Please refer to FIG. 1, which is a schematic structural diagram of a memory system 100 according to some embodiments of the present case. As shown in FIG. 1, the memory system 100 includes a controller 110, a file system 120, a flash translation layer 130, and a memory technology device layer Device Layer) 140, and Flash Memory Chips (Flash Memory Chips) 150. In some embodiments, the controller 110 is used to operate the file system 120, the flash memory conversion layer 130, the memory technology device layer 140, and the flash memory chip 150. The above operations may be, but not limited to, hardware operations, firmware operations, software operations, and combinations thereof.

The controller 110 is coupled to the flash memory chip 150. In one embodiment, the controller 110 is configured to operate the flash memory chip 150 to perform program, read, and erase operations of the flash memory chip 150. In other embodiments, the controller 110 is configured to manage the space allocation usage and the program/erase cycle in the flash memory chip 150. The controller 110 may be, but not limited to, a control circuit or a control chip packaged in a memory chip.

In one embodiment, the flash memory chip 150 is a NAND flash memory chip. The flash memory chip 150 may be, but not limited to, a single-level cell (SLC), a multi-level cell (MLC), a triple-level cell (TLC), or a four-level cell (quad-level cell, QLC) memory chip.

The memory technology device layer 140 is configured to operate on the flash memory conversion layer 130 and the flash memory chip 150. For example, the memory technology device layer 140 may be, but not limited to, firmware for communicating between the flash memory conversion layer 130 and the flash memory chip 150. In some embodiments, the memory technology device layer 140 is used to execute a program procedure 141, a read procedure 143, And erase procedure (erase procedure) 145. In some embodiments, the memory technology device layer 140 stores a rewritable block table. The rewritable block table is used to record the number of times that each page has been rewritten by data. These procedures will be explained in detail in the following pages.

The flash memory conversion layer 130 is configured to perform related software operations on the data of the file system 120. In some embodiments, the flash memory conversion layer 130 includes a write hot/cold data analyzer 131, a garbage collector 133, and a disturbance controller 135.

The write data frequency analyzer 131 is used to analyze the types of data to be written to the flash memory chip 150, such as frequently accessed data (or hot data) and infrequently accessed data (or cold data) )). The method of writing data frequency analyzer 131 to determine the data type can be, but not limited to, using a hash function, least recently used, etc. The disclosed document is not limited to this, other can determine cold data/hot The method of information is also covered in the scope of this disclosure document.

The flash memory chip 150 includes a conventional block region 151 and a rewritable block region 153. In some embodiments, when the written data frequency analyzer 131 analyzes the data as infrequently accessed data, the controller 110 stores the data in the general block range 151 through the programming program 141 of the memory technology device layer 140. In other embodiments, when writing The data frequency analyzer 131 analyzes the data as frequently accessed data, and the controller 110 stores the data in the rewritable block range 153 through the programming program 141 of the memory technology device layer 140.

The memory recycler 133 is configured to manage the block erasing of the flash memory chip 150. In some embodiments, the memory recycler 133 may be a software program, and the controller 110 executes the software program and applies voltage to the flash memory chip 150 to perform data erasing.

The interference processor 135 is configured to manage the disturb status of each page in the flash memory chip 150. In some embodiments, the interference processor 135 may be a software program, and the controller 110 executes the software program to deal with the interference problem of each page.

Please refer to FIG. 2, which is a schematic diagram of rewriting data to a block 200 in the flash memory chip 150 according to the flash memory system 100 shown in FIG. 1. The following is to facilitate the description of the process of rewriting data. In this disclosure, a block contains three pages, and each page contains a memory cell as a description, which is not used in the specific implementation. Limited. For example, a block includes more than three plural pages (for example, 256 pages), and each page includes more than one plural memory units (for example, 32768 memory units) are also covered by the present disclosure.

As shown in FIG. 2, the block 200 includes pages 210, 220, and 230, and word lines WL0, WL1, and WL2. The word line WL0 is used to control the reading and writing of data on the page 210. The character line WL1 is used to control the data reading and writing of the page 220. The character line WL2 is used to control the data reading and writing of the page 230. in In this embodiment, pages 210, 220, and 230 each include a memory unit, where the memory unit is used to store one bit of data.

In an embodiment of the data rewriting procedure, it is suitable for storing hot data. For example, a piece of data has been stored in a page. When this piece of data is updated due to recalculation, the original page will not be erased and written before the updated version of the data is stored. The new version of the data is stored in the page by increasing the voltage level of the stored data.

To explain the data rewriting procedure in more detail, please refer to FIG. 4, which is a flow chart of the steps of the rewriting method according to some embodiments of this case. Also, please refer to the drawings in Figure 1, Figure 2, and Figures 3A~3C for a clear understanding. It is worth mentioning that page 210, page 220, and page 230 in FIG. 2 correspond to word line WL0, word line WL1, and word line WL2, respectively. Page 210 is configured to store the first data A1 and its updated version, page 220 is configured to store the second data B1 and its updated version, and page 230 is configured to store the third data C1 and its updated version. The first data A1 refers to the first version of the first data, the first data A2 refers to the second version of the first data, the first data A3 refers to the third version of the first data, and so on. In some embodiments, the second version of the data is newer than the first version of the data, and the third version of the data is newer than the second version of the data. This disclosure document uses three data updates as an explanation, and the number of data updates is not limited by this.

In step S410, a data is received through the controller 110 And according to the version of the data to save the data on the corresponding page. For example, as shown in FIG. 2, when the first data A1 is ready to be written to the block 200, the controller 110 controls the word line WL0 with the rewrite command RW1 to write the first data A1 to the page 210. When the first data A1 is the first version. In another embodiment, when the first data A2 is ready to be written to the block 200, the controller 110 controls the word line WL0 with the rewrite command RW2 to write the first data A2 to the page 210, and the first data A2 is the second version.

In step S420, a voltage window is added to the threshold voltage as a voltage for writing data. Please refer to Figure 3A. FIG. 3A is a schematic diagram showing the threshold voltage and the number of memory cells of the page 210 in the programming data to the block 200 of FIG. 2 according to some embodiments of the present case. The logic value before the memory cell is written with data is shown in stage RW0, and the memory cell at this time is in the erase state. In one embodiment, the logic value of the memory cell is set to the first logic value, for example 1. When the first data A1 is written to the page 210, as shown in FIG. 3A, the threshold voltage corresponding to the rewrite command RW1 is added to the voltage Vp01. Then, this voltage Vp01 is used as a verification voltage for subsequent verification whether the critical voltage of the memory cell to which data is written is within the expected range. For example, after the first data A1 is written to the page 210 and the threshold voltage is added to the voltage Vp01, the voltage Vp01 is read as a verification voltage to verify whether the first data A1 is correctly written to the page 210. According to this, if it is determined that the threshold voltage of the memory cell of the first data A1 is within the expected range, for example, the voltage Vp01, it is determined that the first data A1 is correctly written to the page 210.

The logic value of the memory cell in a voltage range before the voltage Vp01 is set as the first logic value, for example, 1. The logical value of the memory cell in a voltage range after the voltage Vp01 is set as the second logical value, for example, 0. The first data A1 is stored in the page 210 at this time. When the first data A1 is the latest version of the data, the controller 110 operates the reading program 143 to read the first data A1, which can be read through the reading voltage Vr1 Get the correct version of the information.

By analogy, when the first data A1 is updated to the first data A2, the first data A2 is written to the page 210, as shown in FIG. 3A, the threshold voltage corresponding to the rewrite command RW2 is added to the voltage Vp02 . The logic value of the memory cell in a voltage range before the voltage Vp02 is set as the first logic value, for example 1. The logical value of the memory cell in a voltage range after the voltage Vp02 is set as the second logical value, for example, 0. The first data A2 is stored on the page 210 at this time. When the first data A2 is the latest version of the data, the controller 110 operates the reading program 143 to read the first data A2, which can be read through the reading voltage Vr2 Get the correct version of the information.

In step S430, the data of the previous version is marked as invalid and the data of the new version is marked as valid. For example, as shown in FIG. 2, the controller 110 reads the first data A1 to perform the operation and generates the first data A2. At this time, the first data A2 is the new version of the data, and the first data A1 is the old version of the data, so the first data A2 is marked as valid data (valid data), the first data A1 is marked as invalid data (invalid data) .

In step S440, the controller 110 records the number of times each page has undergone rewriting. For example, in the foregoing step S430, the first data When A1 is updated to the first data A2, the controller 110 records that the number of rewrites of the page 210 is 2 times.

By analogy, if the first data A2 is continuously updated (for example, updated to the first data A3), the content of the new version will be continuously stored on the page 210, and the voltage window Vp02 plus the voltage window according to the rewrite instruction RW3 makes The threshold voltage is added to the voltage Vp03. The logic value of the memory cell in a voltage range before the voltage Vp03 is set as the first logic value, for example 1. The logic value of the memory cell in a voltage range after the voltage Vp03 is set as the second logic value, for example, 0. The first data A3 is marked as valid data, and the first data A2 is marked as invalid data. The controller 110 records that the number of times of rewriting the page 210 is 3 times. The controller 110 can read the correct version of the first data A3 by reading the voltage Vr3.

And, if the first data A3 is updated again (for example, to the first data A4), the content of the new version will be continuously stored on the page 210, and the threshold voltage is added to the voltage Vp03 and the voltage window according to the rewrite instruction RW4 Added to voltage Vp04. The logic value of the memory cell in a voltage range before the voltage Vp04 is set as the first logic value, for example 1. The logic value of the memory cell in a voltage range after the voltage Vp04 is set as the second logic value, for example, 0. The first data A4 is marked as valid data, and the first data A3 is marked as invalid data. The controller 110 records that the number of rewrites of the page 210 is 4 times. The controller 110 can read the correct version of the first data A4 by reading the voltage Vr4.

Therefore, if the structure of the flash memory chip 150 is a four-level cell (QLC), each page can be rewritten up to 15 times material. For example, each memory cell in the memory architecture of a four-level unit has up to 16 voltage states. When repeatedly performing steps S410 to S440, one bit of data can be written to the page each time and a voltage window is incremented to the verification voltage. Therefore, each page can be updated up to 15 times.

When the controller 110 reads the data, it only needs to judge the two voltage states to read the latest version of the data. For example, when the first data A1 is to be read, the controller 110 only needs to control (as shown in FIG. 3A) to read the voltage Vr1 to read the correct data.

It is worth mentioning that the memory technology device layer 140 stores a comparison table, which is used to store the correspondence between each page and the verification voltage, where the verification voltage value corresponds to the latest version of the data. For example, when the latest data stored in the page 210 is the first data A1, the verification voltage corresponding to the page 210 is recorded in the comparison table as the voltage Vp01. When the latest data stored in the page 210 is the first data A2, the verification voltage corresponding to the page 210 is recorded in the comparison table as the voltage Vp02. In this way, the controller 110 obtains the verification voltage value according to the comparison table, and reads the latest version of the data according to the read voltage.

Similarly, selectively repeating steps S410 to S440, the sequence of writing data in the block 200 of FIG. 2 takes the following data sequence as an example: second data B1, second data B2, third data C1, first data A3, first data A4, second data B3, second data B4.

When the second data B1 is ready to be written to the block 200, the controller 110 controls the word line WL2 to rewrite the second data B1 with a rewrite command RW1 Write to page 220, where the second data B1 is the first version.

On the other hand, please refer to Figure 3B. FIG. 3B is a schematic diagram showing the threshold voltage and the number of memory cells of the page 220 in the programming data to the block 200 of FIG. 2 according to some embodiments of the present case. The logic value before the memory cell is written with data is shown in stage RW0, and the memory cell at this time is in the erasing state. In one embodiment, the logic value of the memory cell is set to the first logic value, for example 1. When the second data B1 is written to the page 220, as shown in FIG. 3B, the threshold voltage corresponding to the rewrite command RW1 is added to the voltage Vp11. The logic value of the memory cell in a voltage range before the voltage Vp11 is set as the first logic value, for example, 1. The logic value of the memory cell in a voltage range after the voltage Vp11 is set as the second logic value, for example, 0. The controller 110 records that the number of times of rewriting the page 220 is one.

When the controller 110 reads the data, it only needs to judge the two voltage states to read the latest version of the data. For example, when the second data B1 is to be read, the controller 110 only needs to control (as shown in FIG. 3B) to read the voltage Vr1 to read the correct data. The procedure for updating and reading the second data B1 is similar to the description in FIG. 3A and will not be repeated.

When the third data C1 is ready to be written to the block 200, the controller 110 controls the word line WL3 to write the third data C1 to the page 230 with the rewrite instruction RW1, wherein the third data C1 is the first version.

On the other hand, please refer to Figure 3C. FIG. 3C is a schematic diagram showing the threshold voltage and the number of memory cells of the page 230 in the programming data to the block 200 in FIG. 2 according to some embodiments of the present invention. In mind The logic value before the memory cell is written into the data is shown in stage RW0, at this time the memory cell is in the erased state. In one embodiment, the logic value of the memory cell is set to the first logic value, for example 1. When the third data C1 is written to the page 220, as shown in FIG. 3C, the threshold voltage corresponding to the rewrite command RW1 is added to the voltage Vp21. The logic value of the memory cell in a voltage range before the voltage Vp21 is set as the first logic value, for example, 1. The logical value of the memory cell in a voltage range after the voltage Vp21 is set as the second logical value, for example, 0. The controller 110 records that the number of times of rewriting the page 230 is one.

When the controller 110 reads the data, it only needs to judge the two voltage states to read the latest version of the data. For example, when the third data C1 is to be read, the controller 110 only needs to control (as shown in FIG. 3C) to read the voltage Vr1 to read the correct data.

In the traditional incremental step pulse programming (ISPP) programming method, taking a memory chip with a four-level cell architecture as an example, each memory cell can only be programmed four times. When the written data is hot data, because the hot data only occupies a small part of the total amount of data in the memory, but the nature needs to be updated frequently, so in the traditional programming method, the memory cell that stores the hot data is executed. After four updates, the programming data can no longer be continued, resulting in inefficient use of the entire memory chip. In contrast, the method of rewriting the flash memory chip 150 in this case can increase the number of memory cell updates that store hot data to a maximum of 15 times, which improves the writing efficiency of the memory cell. According to this, compared with the traditional programming method, this case can improve the beneficial effect of data writing efficiency in the memory chip of the multi-level cell structure.

On the other hand, since the number of rewritable times per memory cell increases, in the case of the same program/erase cycle of the memory block, this case can increase the total write bytes of the memory cell (Total Byte Written). In addition, in the case that the total written bytes are the same, this case can reduce the number of erasures of the memory block, which can reduce the strength of the error correction code used in the memory chip to reduce the processing of error correction The cost of the code.

And, the rewriting method of the disclosed document operating on the flash memory chip 150 provides that it is not necessary to erase the old data immediately when the data is updated, but only when the proportion of invalid data in the block is above a certain threshold. Erase the entire block. In this way, the problem of page loss caused by too frequent updating of data on a specific page can be avoided.

In addition, when the controller 110 reads the data, it only needs to judge the two voltage states to read the latest version of the data. Compared with the traditional multi-level cell architecture, the controller 110 needs to record 4 or more verification voltages in order to correctly read the data corresponding to each voltage range. If you are careless about voltage control, you will read Wrong information. This disclosure uses a multi-level unit structure to store the updated content of the same data. One page of data is stored at a time, but multiple updates can be used in the page. In this way, data reading and writing can be reduced Time complexity.

Please refer to FIG. 5, which is a flowchart of steps for performing memory recovery according to some embodiments of the present case. Please refer to Figure 1, Figure 2 and Figure 5 for a clear understanding.

In step S510, the controller 110 uses the block 200, and the memory recycler 133 calculates the size of the invalid space in the block 200.

For example, suppose block 200 includes three pages 210, 220, and 230, and each page includes a memory unit. If the memory cell is a four-level cell (QLC) architecture, each time a bit is stored, a page can be rewritten up to 15 times according to steps S410 to S440 in the aforementioned Figure 4 , Therefore, the total space size is 45 (15*3). On the other hand, in the block 200 of FIG. 2, the valid data is the first data A4, the second data B4, and the third data C1, so the invalid space size is 6 (that is, the aforementioned One data A1, A2, A3 and second data B1, B2, B3).

It is worth mentioning that the rewritable block table in the memory technology device layer 140 records the rewrite count of blocks. For example, the block 200 shown in FIG. 2 has written data 9 times, so the rewrite count of the block 200 is recorded in the rewritable block table as 9. In some embodiments, the rewrite count of block 200 may be, but not limited to, the sum of the rewrite times of page 210, page 220, and page 230.

In step S520, the controller 110 determines whether the ratio of the size of the invalid space in the block 200 to the size of the total space is greater than the efficiency threshold.

As shown in FIG. 2 in the embodiment of block 200, the ratio of the invalid space size to the total space size is about 13%, which means that the remaining available times of the block 200 are still sufficient, and the block 200 can continue to be used. It is worth mentioning that this disclosure does not limit the actual value of the utility threshold. Corresponding numerical settings are made according to the actual situation, for example, the utility threshold is set to 95%, which means that the block 200 is used more frequently. In other embodiments, the controller 110 sets the number of rewritable times of each page of the block 200 to 7 times, and the total space size is 21. As shown in the storage status of the block 200 shown in FIG. 2 (a total of 6 invalid data), the ratio of invalid space to the total space is about 29%. In other words, the setting of the number of times of rewriting of each page can determine the upper limit of the number of times the block is rewritten.

If in step S520, the ratio of the invalid space size to the total space size is not greater than the utility threshold, then return to step S510. If the ratio of the invalid space size to the total space size is greater than the utility threshold, step S530 is executed.

In step S530, the controller 110 programs the valid data in the block 200 to another block (not shown in FIG. 2).

For example, the valid data of the block 200 are the first data A4, the second data B4, and the third data C1. Therefore, this valid data is written to another blank block.

Next, in step S540, the controller 110 marks the block 200 as an invalid block. Therefore, the controller 110 will no longer read the data in the block 200 and no longer write the data in the block 200. In some embodiments, the data in the block 200 is erased only when the space of the block 200 needs to be used.

Please refer to FIG. 6, which is a flowchart of steps of program interference detection according to some embodiments of the present case. Please refer to Figure 1, Figure 2 and Figure 6 together for a clear understanding.

In step S610, the controller 110 programs a data to a page of the block 200. For example, the second data B1 is written into the page 220. The detailed description of this step is as described above.

Next, in step S620, the interference processor 135 increments the disturb factor of other pages (such as page 210 and page 230) adjacent to the page performing data programming in the block 200, and resets the performance factor The interference factor of the page.

For example, taking the first data A1 already stored in the block 200 as an example, no data has been written in the pages 220 and 230. At this time, the interference coefficient of page 210 is reset to 0, and the interference coefficient of page 220 is incremented from 0 to 1 (taking the initial value of the interference coefficient of all blank pages as 0). If the first data A2 is continuously written to the page 210, the interference coefficient of the page 210 is reset to 0, and the interference coefficient of the page 220 is increased from 1 to 2.

Then, when the second data B1 is written to the page 220, the interference coefficients of the pages 210 and 230 adjacent to the page 220 will increase from 0 to 1, respectively. Moreover, the interference coefficient of page 220 will be reset to zero. By analogy, in the embodiment where the order of writing data is <A1, A2, B1, B2, C1, A3, A4, B3, B4>, the interference coefficient of page 210 is 2 and the interference coefficient of page 220 is 0. The interference factor of page 230 is 2.

In step S630, it is determined whether the interference coefficient of each page in the block 200 is greater than a disturbance threshold (disturb threshold).

Taking the interference threshold set to 1 as an example, the interference coefficients of pages 210 and 230 are both greater than the interference threshold.

Next, in step S640, when the interference coefficient of the page is greater than the interference threshold, reprogram the data to the page to reset the interference coefficient of the page.

For example, as shown in FIG. 2, the interference coefficients of page 210 and page 230 are greater than the interference threshold. At this time, the first data A4 will be reprogrammed to page 210 to reset the interference coefficient of page 210. Similarly, the third data C1 will be reprogrammed to the page 230 to reset the interference factor of the page 230.

On the other hand, when the interference coefficient of the page is greater than the interference threshold, step S650 may also be executed. In step S650, when the interference coefficient of the page is greater than the interference threshold, reprogram the data to another page, and mark the page with the interference coefficient greater than the interference threshold as an invalid page.

For example, as shown in FIG. 2, the page 210 stores the first data A4 and the page 230 stores the third data C1. When the interference coefficient of the page 210 is greater than the interference threshold, the first data A4 will be rewritten to another blank page (not shown in FIG. 2), and the page 210 will be marked as an invalid page. Similarly, when the interference factor of the page 230 is greater than the interference threshold, the third data C1 will be written to another blank page (not shown in FIG. 2), and the page 230 will be marked as an invalid page.

It is worth mentioning that, when it is determined in step S630 that the interference coefficient of the page is greater than the interference threshold, step S640 or step S650 may be selectively performed. Both steps S640 and S650 can deal with the problem that the page is too disturbed.

Please refer back to step S630. When the interference coefficient of the page 220 is less than the interference threshold, return to step S610 to continue using the page.

In some embodiments, the present disclosure proposes a non-transitory computer-readable recording medium that can store multiple program codes. After the program code is loaded into the controller 110 as shown in FIG. 1, the controller 110 executes the program code and performs the steps including FIG. 4, FIG. 5, and FIG. 6. For example, the controller 110 receives the data and stores the data in the corresponding page according to the version of the data, increases the voltage window to a critical voltage as the voltage for writing the data, marks the previous version of the data as invalid and marks the new version The information is valid and records the number of times each page has been rewritten.

This disclosed document operates on the flash memory chip 150 programming interference detection method to detect interference detection between adjacent pages to avoid the impact of frequent use of the same data on the same page to maintain other The accuracy of the information on the page.

In summary, the memory management system and memory operation method of the disclosed document consider different storage methods for frequently used data and infrequently used data in the memory chip. For frequently used data to program data with increasing threshold voltage on the same page, the frequency of erasing blocks is reduced, and the availability is improved. The memory recovery and interference detection method of the disclosed document manages the writing method of the memory chip, such as recovering the memory with the minimum number of erasures, and maintaining the accuracy of the memory data. Accordingly, the reading, programming, and erasing of the memory chip can extend the service life of the memory chip.

In addition, the above example includes sequential exemplary steps, but the These steps do not have to be performed in the order shown. Performing these steps in different orders is within the scope of this disclosure. Within the spirit and scope of the embodiments of the present disclosure, the order may be added, replaced, changed, and/or omitted as appropriate.

Although this case has been disclosed as above by way of implementation, it is not intended to limit this case. Anyone who is familiar with this skill can make various changes and modifications within the spirit and scope of this case, so the scope of protection of this case should be considered The scope of the attached patent application shall prevail.

100‧‧‧Memory system

110‧‧‧Controller

120‧‧‧File System

130‧‧‧Flash memory conversion layer

131‧‧‧ Write data frequency analyzer

133‧‧‧Memory Recycler

135‧‧‧ interference processor

140‧‧‧Memory technology device layer

141‧‧‧program

143‧‧‧Reading program

145‧‧‧Erase procedure

150‧‧‧Flash memory chip

151‧‧‧General block range

153‧‧‧ rewritable block range

Claims (10)

A memory system includes: a flash memory chip; and a controller coupled to the flash memory chip, wherein the controller is configured to: receive a first version of a first data from a file system To store the first data of the first version to a first page of the flash memory chip; and in response to a second version of the first data to program the first data of the second version in the The first page, where the second version is newer than the first version. The memory system of claim 1, wherein when the controller programs the second version of the first data on the first page, the controller is further used to: increase a voltage window to a threshold voltage; and Mark the first data of the first version as an invalid data and mark the first data of the second version as a valid data, and increment the first data corresponding to the first page in a rewritable block table One rewrite count for one block. The memory system of claim 2, wherein the controller is further used to calculate an invalid space size in the first block according to the rewrite count, and the controller determines the first area When the ratio of the invalid space of the block to a total space of the first block is greater than a utility threshold, the first data that is valid in the first block is programmed to a second of the flash memory chip Block, and mark the first block as the invalid data. The memory system of claim 1, wherein when the controller programs a second data to a second page of a first block, the controller is also used to increment a first of the first block An interference coefficient of a page, and when the interference coefficient of the first page is greater than an interference threshold, the controller is also used to reprogram the first data to the first page to reset the interference of the first page coefficient. The memory system of claim 1, wherein when the controller programs a second data to a second page of a first block, the controller is also used to increment a first page of the first block An interference coefficient, and when the interference coefficient of the first page is greater than an interference threshold, the controller is also used to reprogram the first data to a third page of the first block and mark the first One page is invalid data. A memory operation method includes: receiving a first data of a first version from a file system to store the first data of the first version to a through a controller A first page of a flash memory chip; and in response to a second version of the first data, programming the second version of the first data on the first page through the controller, wherein the second version is new For the first version. The memory operation method according to claim 6, wherein programming the first data of the second version on the first page further comprises: adding a voltage window to a threshold voltage; and marking the first version of the first version The data is an invalid data, and the first data of the second version is marked as a valid data, and a rewrite count corresponding to a first block where the first page is located is incremented in a rewritable block table . The memory operation method according to claim 7, further comprising: calculating an invalid space in the first block according to the rewrite count; and determining that the invalid space of the first block occupies the first block When a proportion of a total space size is greater than a utility threshold, program the first data valid in the first block to a second block of the flash memory chip, and mark the first block as The invalid data. The memory operation method according to claim 6, further comprising: when a second data is programmed to a second page of a first block, incrementing an interference coefficient of a first page of the first block , And when the interference coefficient of the first page is greater than an interference threshold, reprogram the first data to the first page to reset the interference coefficient of the first page. The memory operation method according to claim 6, further comprising: when a second data is programmed to a second page of a first block, incrementing an interference coefficient of a first page of the first block , And when the interference coefficient of the first page is greater than an interference threshold, reprogram the first data to a third page of the first block; and mark the first page as an invalid data.

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