TWI694449B - Memory system and method of operating memory - Google Patents

Memory system and method of operating memory Download PDF

Info

Publication number
TWI694449B
TWI694449B TW108133277A TW108133277A TWI694449B TW I694449 B TWI694449 B TW I694449B TW 108133277 A TW108133277 A TW 108133277A TW 108133277 A TW108133277 A TW 108133277A TW I694449 B TWI694449 B TW I694449B
Authority
TW
Taiwan
Prior art keywords
data
page
block
version
controller
Prior art date
Application number
TW108133277A
Other languages
Chinese (zh)
Other versions
TW202113850A (en
Inventor
林秉賢
王韋程
李祥邦
廖書賢
曹哲維
張原豪
郭大維
Original Assignee
旺宏電子股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 旺宏電子股份有限公司 filed Critical 旺宏電子股份有限公司
Priority to TW108133277A priority Critical patent/TWI694449B/en
Application granted granted Critical
Publication of TWI694449B publication Critical patent/TWI694449B/en
Publication of TW202113850A publication Critical patent/TW202113850A/en

Links

Images

Abstract

The present disclosure provides a memory system and a method of operating memory. The memory system includes a flash memory chip and a controller. The controller is coupled with the flash memory chip, which the controller is configured to: receive a data with a first version from a file system in order to store the data corresponding to the first version in a first page of the flash memory chip; and program the data corresponding to a second version in the first page in response to the second version of the data, which the second version is newer than the first version.

Description

記憶體系統以及記憶體操作方法 Memory system and memory operation method

本揭示文件係有關於一種記憶體及其操作方法,且特別是有關於一種記憶體系統及操作記憶體方法。 The present disclosure relates to a memory and its operating method, and particularly to a memory system and a method of operating the memory.

基於快閃記憶體之硬體上的特性,對於資料的寫入(program)及抹除(erase)次數方面需要嚴謹的管理。一方面來說,在快閃記憶體中頻繁地讀寫時,往往會加速電子元件的使用壽命下降。另一方面,為提升快閃記憶體的資料密度,多級單元(multi-level cell)的架構亦被提出,使得一個記憶單元中可以儲存多個位元。在多級單元的架構中,雖然可以讓可儲存的資料量上升而降低了硬體成本,然而,這樣的架構卻相對地提高了錯誤更正碼(error correcting code)的要求。 Based on the characteristics of the flash memory hardware, strict management is required for the number of data writes and erases. On the one hand, when reading and writing frequently in the flash memory, the service life of electronic components is often reduced. On the other hand, in order to improve the data density of flash memory, a multi-level cell (multi-level cell) architecture has also been proposed, so that a memory cell can store multiple bits. In the multi-level unit architecture, although the amount of storable data can be increased to reduce the hardware cost, this architecture has relatively increased the requirements for error correcting codes.

有鑑於此,基於快閃記憶體的電子特性條件下,如何有效地克服使用壽命下降及降低錯誤更正的要求,係亟需解決的問題。 In view of this, based on the electronic characteristics of flash memory, how to effectively overcome the requirements of reduced service life and reduced error correction is an urgent problem to be solved.

本案之一態樣是在提供一種記憶體系統,包含一快閃記憶體晶片以及一控制器。控制器耦接該快閃記憶體晶片,其中該控制器經配置以自一檔案系統接收一第一版本之一資料,以儲存該第一版本之該資料至該快閃記憶體晶片之一第一頁面;以及響應於該資料之一第二版本以編程該第二版本之該資料於該第一頁面,其中該第二版本新於該第一版本。 One aspect of this case is to provide a memory system including a flash memory chip and a controller. The controller is coupled to the flash memory chip, wherein the controller is configured to receive a data of a first version from a file system to store the data of the first version to a first of the flash memory chip A page; and in response to a second version of the data to program the second version of the data on the first page, wherein the second version is newer than the first version.

本案之一態樣是在提供一種記憶體操作方法。記憶體操作方法包含以下步驟:自一檔案系統接收一第一版本之一資料,以透過一控制器儲存該第一版本之該資料至一快閃記憶體晶片之一第一頁面;以及響應於該資料之一第二版本,透過該控制器編程該第二版本之該資料於該第一頁面,其中該第二版本新於該第一版本。 One aspect of this case is to provide a memory operation method. The memory operation method includes the following steps: receiving data of a first version from a file system to store the data of the first version to a first page of a flash memory chip through a controller; and responding A second version of the data, the second version of the data is programmed on the first page by the controller, wherein the second version is newer than the first version.

100‧‧‧記憶體系統 100‧‧‧Memory system

110‧‧‧控制器 110‧‧‧Controller

120‧‧‧檔案系統 120‧‧‧File System

130‧‧‧快閃記憶體轉換層 130‧‧‧Flash memory conversion layer

131‧‧‧寫入資料頻率分析器 131‧‧‧ Write data frequency analyzer

133‧‧‧記憶體回收器 133‧‧‧Memory Recycler

135‧‧‧干擾處理器 135‧‧‧ interference processor

140‧‧‧記憶體技術裝置層 140‧‧‧Memory technology device layer

141‧‧‧編程程序 141‧‧‧program

143‧‧‧讀取程序 143‧‧‧Reading program

145‧‧‧抹除程序 145‧‧‧Erase procedure

150‧‧‧快閃記憶體晶片 150‧‧‧Flash memory chip

151‧‧‧一般區塊範圍 151‧‧‧General block range

153‧‧‧可重寫區塊範圍 153‧‧‧ rewritable block range

200‧‧‧區塊 200‧‧‧ block

210、220、230‧‧‧頁面 210, 220, 230‧‧‧ page

RW0、RW1、RW2、RW3、RW4‧‧‧重寫指令 RW0, RW1, RW2, RW3, RW4

WL0、WL1、WL2‧‧‧字元線 WL0, WL1, WL2 ‧‧‧ character line

A1~A4、B1~B4、C1‧‧‧資料 A1~A4, B1~B4, C1‧‧‧ data

Vt‧‧‧臨界電壓 Vt‧‧‧critical voltage

Vp01、Vp02、Vp03、Vp04‧‧‧電壓 Vp01, Vp02, Vp03, Vp04 ‧‧‧ voltage

Vp11‧‧‧電壓 Vp11‧‧‧Voltage

Vp21‧‧‧電壓 Vp21‧‧‧Voltage

Vr1~Vr4‧‧‧讀取電壓 Vr1~Vr4‧‧‧Read voltage

S410~S440、S510~S540、S610~S660‧‧‧步驟 S410~S440, S510~S540, S610~S660

為讓本案之上述和其他目的、特徵、優點與實施例能更明顯易懂,所附圖式之說明如下:第1圖係根據本案之一些實施例所繪示之一種記憶體系統之架構示意圖。 In order to make the above and other purposes, features, advantages and embodiments of the present case more obvious and understandable, the drawings are described as follows: Figure 1 is a schematic diagram of the architecture of a memory system according to some embodiments of the present case .

第2圖係根據第1圖之快閃記憶體系統所繪示之重寫資料至快閃記憶體晶片中一區塊之示意圖。 FIG. 2 is a schematic diagram of rewriting data to a block in the flash memory chip according to the flash memory system shown in FIG.

第3A圖係根據本案之一些實施例所繪示於編程資 料至第2圖之區塊中的頁面的臨界電壓與記憶胞數量之示意圖。 Figure 3A is shown in the programming resources according to some embodiments of the case A schematic diagram of the threshold voltage and the number of memory cells of the page in the block in FIG. 2 is expected.

第3B圖係根據本案之一些實施例所繪示於編程資料至第2圖之區塊中的頁面的臨界電壓與記憶胞數量之示意圖。 FIG. 3B is a schematic diagram showing the threshold voltage and the number of memory cells of the pages in the programming data to the block in FIG. 2 according to some embodiments of the present case.

第3C圖係根據本案之一些實施例所繪示於編程資料至第2圖之區塊中的頁面的臨界電壓與記憶胞數量之示意圖。 FIG. 3C is a schematic diagram showing the critical voltage and the number of memory cells of the pages in the programming data to the block in FIG. 2 according to some embodiments of the present case.

第4圖係根據本案之一些實施例所繪示之重新寫入方法之步驟流程圖。 FIG. 4 is a flowchart of steps of a rewriting method according to some embodiments of the present case.

第5圖係根據本案之一些實施例所繪示之執行記憶體回收之步驟流程圖。 FIG. 5 is a flowchart of steps for performing memory recovery according to some embodiments of the present case.

第6圖係根據本案之一些實施例所繪示之編程干擾偵測之步驟流程圖。 FIG. 6 is a flowchart showing the steps of programming interference detection according to some embodiments of the present case.

以下揭示提供許多不同實施例或例證用以實施本案的不同特徵。特殊例證中的元件及配置在以下討論中被用來簡化本揭示。所討論的任何例證只用來作解說的用途,並不會以任何方式限制本案或其例證之範圍和意義。此外,本揭示在不同例證中可能重複引用數字符號且/或字母,這些重複皆為了簡化及闡述,其本身並未指定以下討論中不同實施例且/或配置之間的關係。 The following disclosure provides many different embodiments or illustrations to implement the different features of this case. The elements and configurations in the specific illustrations are used to simplify this disclosure in the following discussion. Any illustrations discussed are for illustrative purposes only and do not limit the scope and significance of the case or its illustrations in any way. In addition, the present disclosure may repeatedly refer to numerical symbols and/or letters in different illustrations. These repetitions are for simplicity and explanation, and do not specify the relationship between different embodiments and/or configurations in the following discussion.

在全篇說明書與申請專利範圍所使用之用 詞(terms),除有特別註明外,通常具有每個用詞使用在此領域中、在此揭露之內容中與特殊內容中的平常意義。某些用以描述本揭露之用詞將在此說明書的別處討論,以提供本領域技術人員在有關本揭露之描述上額外的引導。 Used in the entire specification and patent application scope Terms (terms), unless otherwise noted, usually have the usual meaning that each word is used in this field, in the content disclosed here, and in special content. Certain terms used to describe this disclosure will be discussed elsewhere in this specification to provide additional guidance to those skilled in the art in the description of this disclosure.

關於本文中所使用之『耦接』或『連接』,均可指二或多個元件相互直接作實體或電性接觸,或是相互間接作實體或電性接觸,而『耦接』或『連接』還可指二或多個元件相互操作或動作。 With regard to "coupling" or "connection" used in this article, it can mean that two or more components directly make physical or electrical contact with each other, or indirectly make physical or electrical contact with each other, while "coupled" or "connected" "Connected" may also refer to the interoperation or movement of two or more elements.

在本文中,使用第一、第二與第三等等之詞彙,是用於描述各種元件、組件、區域、層與/或區塊是可以被理解的。但是這些元件、組件、區域、層與/或區塊不應該被這些術語所限制。這些詞彙只限於用來辨別單一元件、組件、區域、層與/或區塊。因此,在下文中的第一元件、組件、區域、層與/或區塊也可被稱為第二元件、組件、區域、層與/或區塊,而不脫離本案的本意。 In this document, the terms first, second, third, etc. are used to describe various elements, components, regions, layers, and/or blocks that can be understood. But these elements, components, regions, layers and/or blocks should not be limited by these terms. These words are only used to identify a single element, component, region, layer and/or block. Therefore, the first element, component, region, layer, and/or block in the following may also be referred to as the second element, component, region, layer, and/or block, without departing from the original intention of this case.

值得一提的是,在本揭示文件中,用語「儲存」、「寫入」及「編程」可交換地使用,在意思表示上應被理解為相同意義而不致產生歧異。 It is worth mentioning that, in this disclosure, the terms "save", "write" and "program" are used interchangeably, and the meaning should be understood as the same meaning without ambiguity.

請參照第1圖,其係根據本案之一些實施例所繪示之一種記憶體系統100之架構示意圖。如第1圖所示,記憶體系統100包含控制器110、檔案系統(File Systems)120、快閃記憶體轉換層(Flash Translation Layer)130、記憶體技術裝置層(Memory Technology Device Layer)140、以及快閃記憶體晶片(Flash Memory Chips)150。在一些實施例中,控制器110用於操作檔案系統120、快閃記憶體轉換層130、記憶體技術裝置層140、以及快閃記憶體晶片150之運作。上述之操作可以為但不限於硬體操作、韌體操作、軟體操作及其組合。 Please refer to FIG. 1, which is a schematic structural diagram of a memory system 100 according to some embodiments of the present case. As shown in FIG. 1, the memory system 100 includes a controller 110, a file system 120, a flash translation layer 130, and a memory technology device layer Device Layer) 140, and Flash Memory Chips (Flash Memory Chips) 150. In some embodiments, the controller 110 is used to operate the file system 120, the flash memory conversion layer 130, the memory technology device layer 140, and the flash memory chip 150. The above operations may be, but not limited to, hardware operations, firmware operations, software operations, and combinations thereof.

控制器110耦接於快閃記憶體晶片150。在一實施例中,控制器110經配置以操作快閃記憶體晶片150,以執行快閃記憶體晶片150的編程(program)、讀取(read)、以及抹除(erase)。在另一些實施例中,控制器110經配置以管理快閃記憶體晶片150中的空間分配使用以及抹寫次數(program/erase cycle)。控制器110可以為但不限於封裝在記憶體晶片中的控制電路或控制晶片。 The controller 110 is coupled to the flash memory chip 150. In one embodiment, the controller 110 is configured to operate the flash memory chip 150 to perform program, read, and erase operations of the flash memory chip 150. In other embodiments, the controller 110 is configured to manage the space allocation usage and the program/erase cycle in the flash memory chip 150. The controller 110 may be, but not limited to, a control circuit or a control chip packaged in a memory chip.

在一實施例中,快閃記憶體晶片150為反及閘型(NAND)快閃記憶體晶片。快閃記憶體晶片150可以為但不限於使用單級單元(single-level cell,SLC)、多級單元(multi-level,MLC)、三級單元(triple-level cell,TLC)、四級單元(quad-level cell,QLC)架構之記憶體晶片。 In one embodiment, the flash memory chip 150 is a NAND flash memory chip. The flash memory chip 150 may be, but not limited to, a single-level cell (SLC), a multi-level cell (MLC), a triple-level cell (TLC), or a four-level cell (quad-level cell, QLC) memory chip.

記憶體技術裝置層140經配置以操作於快閃記憶體轉換層130與快閃記憶體晶片150。舉例來說,記憶體技術裝置層140可以為但不限於用於在快閃記憶體轉換層130與快閃記憶體晶片150之間溝通的韌體。在一些實施例中,記憶體技術裝置層140用以執行編程程序(program procedure)141、讀取程序(read procedure)143、 以及抹除程序(erase procedure)145。在一些實施例中,記憶體技術裝置層140中儲存可重寫區塊表(rewritable block table),可重寫區塊表用以記錄各頁面已被執行資料重寫的次數。此些程序將於後續篇幅作詳細說明。 The memory technology device layer 140 is configured to operate on the flash memory conversion layer 130 and the flash memory chip 150. For example, the memory technology device layer 140 may be, but not limited to, firmware for communicating between the flash memory conversion layer 130 and the flash memory chip 150. In some embodiments, the memory technology device layer 140 is used to execute a program procedure 141, a read procedure 143, And erase procedure (erase procedure) 145. In some embodiments, the memory technology device layer 140 stores a rewritable block table. The rewritable block table is used to record the number of times that each page has been rewritten by data. These procedures will be explained in detail in the following pages.

快閃記憶體轉換層130經配置以對檔案系統120的資料執行相關的軟體操作。在一些實施例中,快閃記憶體轉換層130包含寫入資料頻率分析器(write hot/cold data analyzer)131、記憶體回收器(garbage collector)133、以及干擾處理器(disturbance controller)135。 The flash memory conversion layer 130 is configured to perform related software operations on the data of the file system 120. In some embodiments, the flash memory conversion layer 130 includes a write hot/cold data analyzer 131, a garbage collector 133, and a disturbance controller 135.

寫入資料頻率分析器131用以分析將寫入快閃記憶體晶片150的資料類型,例如經常存取資料(或熱資料(hot data))以及不常存取資料(或冷資料(cold data))。寫入資料頻率分析器131判斷資料類型的方式可以為但不限於使用雜湊函數(hash function)、最近最少使用(least recently used)等方法,本揭示文件不限於此,其他可判斷冷資料/熱資料的方法亦涵蓋在本揭示文件之範疇。 The write data frequency analyzer 131 is used to analyze the types of data to be written to the flash memory chip 150, such as frequently accessed data (or hot data) and infrequently accessed data (or cold data) )). The method of writing data frequency analyzer 131 to determine the data type can be, but not limited to, using a hash function, least recently used, etc. The disclosed document is not limited to this, other can determine cold data/hot The method of information is also covered in the scope of this disclosure document.

快閃記憶體晶片150包含一般區塊範圍(traditional block region)151以及可重寫區塊範圍(rewritable block region)153。在一些實施例中,當寫入資料頻率分析器131分析出資料為不常存取資料,控制器110透過記憶體技術裝置層140之編程程序141將資料儲存於一般區塊範圍151。在另一些實施例中,當寫入 資料頻率分析器131分析出資料為經常存取資料,控制器110透過記憶體技術裝置層140之編程程序141將資料儲存於可重寫區塊範圍153。 The flash memory chip 150 includes a conventional block region 151 and a rewritable block region 153. In some embodiments, when the written data frequency analyzer 131 analyzes the data as infrequently accessed data, the controller 110 stores the data in the general block range 151 through the programming program 141 of the memory technology device layer 140. In other embodiments, when writing The data frequency analyzer 131 analyzes the data as frequently accessed data, and the controller 110 stores the data in the rewritable block range 153 through the programming program 141 of the memory technology device layer 140.

記憶體回收器133經配置以管理快閃記憶體晶片150的區塊抹除。在一些實施例中,記憶體回收器133可以為一軟體程序,而由控制器110來執行軟體程序並對快閃記憶體晶片150施加電壓以執行資料抹除。 The memory recycler 133 is configured to manage the block erasing of the flash memory chip 150. In some embodiments, the memory recycler 133 may be a software program, and the controller 110 executes the software program and applies voltage to the flash memory chip 150 to perform data erasing.

干擾處理器135經配置以管理快閃記憶體晶片150中的各頁面之受干擾(disturb)情況。在一些實施例中,干擾處理器135可以為一軟體程序,而由控制器110來執行軟體程序以處理各頁面的干擾問題。 The interference processor 135 is configured to manage the disturb status of each page in the flash memory chip 150. In some embodiments, the interference processor 135 may be a software program, and the controller 110 executes the software program to deal with the interference problem of each page.

請參照第2圖,其係根據第1圖之快閃記憶體系統100所繪示之重寫資料至快閃記憶體晶片150中一區塊200之示意圖。以下為便於說明重寫資料之程序,本揭示文件中係以一個區塊包含三個頁面(page),其中每個頁面包含一個記憶單元(memory cell)作為說明,於具體實施上並不以此為限。舉例來說,一個區塊包含三個以上的複數個頁面(例如256個頁面),並且每個頁面包含一個以上的複數個記憶單元(例如32768個記憶單元)亦在本揭示文件的涵蓋範圍。 Please refer to FIG. 2, which is a schematic diagram of rewriting data to a block 200 in the flash memory chip 150 according to the flash memory system 100 shown in FIG. 1. The following is to facilitate the description of the process of rewriting data. In this disclosure, a block contains three pages, and each page contains a memory cell as a description, which is not used in the specific implementation. Limited. For example, a block includes more than three plural pages (for example, 256 pages), and each page includes more than one plural memory units (for example, 32768 memory units) are also covered by the present disclosure.

如第2圖所示,區塊200包含頁面210、220、230,以及字元線WL0、WL1、WL2。字元線WL0用以控制頁面210的資料讀寫。字元線WL1用以控制頁面220的資料讀寫。字元線WL2用以控制頁面230的資料讀寫。在 此實施例中,頁面210、220、230分別包含一個記憶單元,其中該記憶單元用以儲存一個位元的資料。 As shown in FIG. 2, the block 200 includes pages 210, 220, and 230, and word lines WL0, WL1, and WL2. The word line WL0 is used to control the reading and writing of data on the page 210. The character line WL1 is used to control the data reading and writing of the page 220. The character line WL2 is used to control the data reading and writing of the page 230. in In this embodiment, pages 210, 220, and 230 each include a memory unit, where the memory unit is used to store one bit of data.

在資料重寫之程序的一實施例中,適用於儲存經常存取資料(hot data)。舉例來說,在一頁面中已儲存有一筆資料,當此筆資料因為重新運算而產生更新的版本時,在儲存此更新版本的資料之前並不會對原本頁面進行抹除後寫入,而是透過增加儲存資料的電壓位準方式來將新版本的資料儲存於頁面中。 In an embodiment of the data rewriting procedure, it is suitable for storing hot data. For example, a piece of data has been stored in a page. When this piece of data is updated due to recalculation, the original page will not be erased and written before the updated version of the data is stored. The new version of the data is stored in the page by increasing the voltage level of the stored data.

為更詳細地說明資料重寫之程序,請參照第4圖,其係根據本案之一些實施例所繪示之重新寫入方法之步驟流程圖。並且,請一併參照第1圖、第2圖、第3A~3C圖的圖式以得到清楚的理解。值得一提的是,第2圖中的頁面210、頁面220、及頁面230分別對應於字元線WL0、字元線WL1、及字元線WL2。頁面210經配置以儲存第一資料A1及其更新版本,頁面220經配置以儲存第二資料B1及其更新版本,頁面230經配置以儲存第三資料C1及其更新版本。其中第一資料A1係指第一資料的第一版本,第一資料A2係指第一資料的第二版本,第一資料A3係指第一資料的第三版本,以此類推。在一些實施例中,第二版本的資料較新於第一版本的資料,第三版本的資料較新於第二版本的資料。本揭示文件以三次的資料更新作為說明,資料更新的次數不因此而受到限制。 To explain the data rewriting procedure in more detail, please refer to FIG. 4, which is a flow chart of the steps of the rewriting method according to some embodiments of this case. Also, please refer to the drawings in Figure 1, Figure 2, and Figures 3A~3C for a clear understanding. It is worth mentioning that page 210, page 220, and page 230 in FIG. 2 correspond to word line WL0, word line WL1, and word line WL2, respectively. Page 210 is configured to store the first data A1 and its updated version, page 220 is configured to store the second data B1 and its updated version, and page 230 is configured to store the third data C1 and its updated version. The first data A1 refers to the first version of the first data, the first data A2 refers to the second version of the first data, the first data A3 refers to the third version of the first data, and so on. In some embodiments, the second version of the data is newer than the first version of the data, and the third version of the data is newer than the second version of the data. This disclosure document uses three data updates as an explanation, and the number of data updates is not limited by this.

在步驟S410中,透過控制器110接收一資料 並根據資料之版本來儲存資料於對應之頁面。舉例來說,如第2圖所示,當第一資料A1準備被寫入至區塊200時,控制器110以重寫指令RW1控制字元線WL0將第一資料A1寫入頁面210,此時第一資料A1為第一版本。在另一實施例中,當第一資料A2準備被寫入至區塊200時,控制器110以重寫指令RW2控制字元線WL0將第一資料A2寫入頁面210,此時第一資料A2為第二版本。 In step S410, a data is received through the controller 110 And according to the version of the data to save the data on the corresponding page. For example, as shown in FIG. 2, when the first data A1 is ready to be written to the block 200, the controller 110 controls the word line WL0 with the rewrite command RW1 to write the first data A1 to the page 210. When the first data A1 is the first version. In another embodiment, when the first data A2 is ready to be written to the block 200, the controller 110 controls the word line WL0 with the rewrite command RW2 to write the first data A2 to the page 210, and the first data A2 is the second version.

在步驟S420中,增加一電壓視窗(voltage window)至臨界電壓,以作為寫入資料的電壓。請參照第3A圖。第3A圖係根據本案之一些實施例所繪示於編程資料至第2圖之區塊200中的頁面210的臨界電壓與記憶胞數量之示意圖。在記憶胞被寫入資料之前的邏輯值如階段RW0所示,此時的記憶胞為抹除(erase)狀態。在一實施例中,記憶胞的邏輯值被設定為第一邏輯值,例如1。在第一資料A1被寫入頁面210時,如第3A圖所示,對應至重寫指令RW1的臨界電壓被新增至電壓Vp01。接著,此電壓Vp01被作為驗證電壓,以供後續驗證寫入資料的記憶胞的臨界電壓是否位於預期的範圍內。舉例來說,在第一資料A1被寫入頁面210以及臨界電壓被新增至電壓Vp01之後,此電壓Vp01會被作為驗證電壓進行讀取,以驗證第一資料A1是否被正確地寫入頁面210。據此,若經判斷第一資料A1的記憶胞的臨界電壓位於預期的範圍內,例如電壓Vp01,則判斷第一資料A1被正確地寫入頁面210。 In step S420, a voltage window is added to the threshold voltage as a voltage for writing data. Please refer to Figure 3A. FIG. 3A is a schematic diagram showing the threshold voltage and the number of memory cells of the page 210 in the programming data to the block 200 of FIG. 2 according to some embodiments of the present case. The logic value before the memory cell is written with data is shown in stage RW0, and the memory cell at this time is in the erase state. In one embodiment, the logic value of the memory cell is set to the first logic value, for example 1. When the first data A1 is written to the page 210, as shown in FIG. 3A, the threshold voltage corresponding to the rewrite command RW1 is added to the voltage Vp01. Then, this voltage Vp01 is used as a verification voltage for subsequent verification whether the critical voltage of the memory cell to which data is written is within the expected range. For example, after the first data A1 is written to the page 210 and the threshold voltage is added to the voltage Vp01, the voltage Vp01 is read as a verification voltage to verify whether the first data A1 is correctly written to the page 210. According to this, if it is determined that the threshold voltage of the memory cell of the first data A1 is within the expected range, for example, the voltage Vp01, it is determined that the first data A1 is correctly written to the page 210.

電壓Vp01之前的一電壓範圍的記憶胞的邏輯值設為第一邏輯值,例如1。電壓Vp01之後的一電壓範圍的記憶胞的邏輯值設為第二邏輯值,例如0。第一資料A1此時被儲存在頁面210,在第一資料A1為最新版本的資料之情況下,控制器110操作讀取程序143以讀取第一資料A1時,可以透過讀取電壓Vr1讀取到正確版本的資料。 The logic value of the memory cell in a voltage range before the voltage Vp01 is set as the first logic value, for example, 1. The logical value of the memory cell in a voltage range after the voltage Vp01 is set as the second logical value, for example, 0. The first data A1 is stored in the page 210 at this time. When the first data A1 is the latest version of the data, the controller 110 operates the reading program 143 to read the first data A1, which can be read through the reading voltage Vr1 Get the correct version of the information.

以此類推,當第一資料A1被更新為第一資料A2時,第一資料A2被寫入頁面210,如第3A圖所示,對應至重寫指令RW2的臨界電壓被新增至電壓Vp02。電壓Vp02之前的一電壓範圍的記憶胞的邏輯值設為第一邏輯值,例如1。電壓Vp02之後的一電壓範圍的記憶胞的邏輯值設為第二邏輯值,例如0。第一資料A2此時被儲存在頁面210,在第一資料A2為最新版本的資料之情況下,控制器110操作讀取程序143以讀取第一資料A2時,可以透過讀取電壓Vr2讀取到正確版本的資料。 By analogy, when the first data A1 is updated to the first data A2, the first data A2 is written to the page 210, as shown in FIG. 3A, the threshold voltage corresponding to the rewrite command RW2 is added to the voltage Vp02 . The logic value of the memory cell in a voltage range before the voltage Vp02 is set as the first logic value, for example 1. The logical value of the memory cell in a voltage range after the voltage Vp02 is set as the second logical value, for example, 0. The first data A2 is stored on the page 210 at this time. When the first data A2 is the latest version of the data, the controller 110 operates the reading program 143 to read the first data A2, which can be read through the reading voltage Vr2 Get the correct version of the information.

在步驟S430中,標記前一版本的資料為無效及標記新版本的資料為有效。舉例來說,如第2圖所示,控制器110讀取第一資料A1以執行運算後產生第一資料A2。此時,第一資料A2為新版本之資料,而第一資料A1為舊版本之資料,因此標記第一資料A2為有效資料(valid data),標記第一資料A1為無效資料(invalid data)。 In step S430, the data of the previous version is marked as invalid and the data of the new version is marked as valid. For example, as shown in FIG. 2, the controller 110 reads the first data A1 to perform the operation and generates the first data A2. At this time, the first data A2 is the new version of the data, and the first data A1 is the old version of the data, so the first data A2 is marked as valid data (valid data), the first data A1 is marked as invalid data (invalid data) .

在步驟S440中,控制器110會記錄各頁面經歷重寫的次數。舉例來說,在前述步驟S430中第一資料 A1更新為第一資料A2時,控制器110會記錄頁面210的重寫次數為2次。 In step S440, the controller 110 records the number of times each page has undergone rewriting. For example, in the foregoing step S430, the first data When A1 is updated to the first data A2, the controller 110 records that the number of rewrites of the page 210 is 2 times.

以此類推,若第一資料A2持續被更新(例如更新為第一資料A3),則新版本的內容將被持續儲存於頁面210,以及根據重寫指令RW3在電壓Vp02加上電壓視窗而使得臨界電壓新增至電壓Vp03。電壓Vp03之前的一電壓範圍的記憶胞的邏輯值設為第一邏輯值,例如1。電壓Vp03後的一電壓範圍的記憶胞的邏輯值設為第二邏輯值,例如0。第一資料A3被標記為有效資料,第一資料A2被標記為無效資料。控制器110會記錄頁面210的重寫次數為3次。控制器110可以透過讀取電壓Vr3以讀取到正確版本的第一資料A3。 By analogy, if the first data A2 is continuously updated (for example, updated to the first data A3), the content of the new version will be continuously stored on the page 210, and the voltage window Vp02 plus the voltage window according to the rewrite instruction RW3 makes The threshold voltage is added to the voltage Vp03. The logic value of the memory cell in a voltage range before the voltage Vp03 is set as the first logic value, for example 1. The logic value of the memory cell in a voltage range after the voltage Vp03 is set as the second logic value, for example, 0. The first data A3 is marked as valid data, and the first data A2 is marked as invalid data. The controller 110 records that the number of times of rewriting the page 210 is 3 times. The controller 110 can read the correct version of the first data A3 by reading the voltage Vr3.

以及,若第一資料A3再次被更新(例如更新為第一資料A4),則新版本的內容將被持續儲存於頁面210,以及根據重寫指令RW4在電壓Vp03加上電壓視窗而使得臨界電壓新增至電壓Vp04。電壓Vp04之前的一電壓範圍的記憶胞的邏輯值設為第一邏輯值,例如1。電壓Vp04之後的一電壓範圍的記憶胞的邏輯值設為第二邏輯值,例如0。第一資料A4被標記為有效資料,第一資料A3被標記為無效資料。控制器110會記錄頁面210的重寫次數為4次。控制器110可以透過讀取電壓Vr4以讀取到正確版本的第一資料A4。 And, if the first data A3 is updated again (for example, to the first data A4), the content of the new version will be continuously stored on the page 210, and the threshold voltage is added to the voltage Vp03 and the voltage window according to the rewrite instruction RW4 Added to voltage Vp04. The logic value of the memory cell in a voltage range before the voltage Vp04 is set as the first logic value, for example 1. The logic value of the memory cell in a voltage range after the voltage Vp04 is set as the second logic value, for example, 0. The first data A4 is marked as valid data, and the first data A3 is marked as invalid data. The controller 110 records that the number of rewrites of the page 210 is 4 times. The controller 110 can read the correct version of the first data A4 by reading the voltage Vr4.

因此,若快閃記憶體晶片150的架構為四級單元(QLC),則每個頁面最多可以重新寫入15次的資 料。舉例來說,四級單元之記憶體架構中的每個記憶細胞最多有16種電壓狀態。於重複執行步驟S410~步驟S440時,每次可在頁面寫入1個位元的資料並遞增一電壓視窗至驗證電壓。因此,每個頁面最多可被更新15次的資料。 Therefore, if the structure of the flash memory chip 150 is a four-level cell (QLC), each page can be rewritten up to 15 times material. For example, each memory cell in the memory architecture of a four-level unit has up to 16 voltage states. When repeatedly performing steps S410 to S440, one bit of data can be written to the page each time and a voltage window is incremented to the verification voltage. Therefore, each page can be updated up to 15 times.

在控制器110讀取資料時,只需判斷兩種電壓狀態即可讀取到最新版本的資料。舉例來說,第一資料A1將被讀取時,控制器110只需控制以(如第3A圖所示)讀取電壓Vr1之電壓即可讀到正確的資料。 When the controller 110 reads the data, it only needs to judge the two voltage states to read the latest version of the data. For example, when the first data A1 is to be read, the controller 110 only needs to control (as shown in FIG. 3A) to read the voltage Vr1 to read the correct data.

值得一提的是,記憶體技術裝置層140中儲存有一對照表,此對照表用來儲存各頁面以及驗證電壓的對應關係,其中驗證電壓值係對應至最新版本的資料。舉例來說,當頁面210中儲存之最新資料為第一資料A1,則對照表中記錄對應於頁面210的驗證電壓為電壓Vp01。當頁面210中儲存之最新資料為第一資料A2,則對照表中記錄對應於頁面210的驗證電壓為電壓Vp02。如此一來,控制器110依據對照表中取得驗證電壓值,並根據讀取電壓讀取到最新版本的資料。 It is worth mentioning that the memory technology device layer 140 stores a comparison table, which is used to store the correspondence between each page and the verification voltage, where the verification voltage value corresponds to the latest version of the data. For example, when the latest data stored in the page 210 is the first data A1, the verification voltage corresponding to the page 210 is recorded in the comparison table as the voltage Vp01. When the latest data stored in the page 210 is the first data A2, the verification voltage corresponding to the page 210 is recorded in the comparison table as the voltage Vp02. In this way, the controller 110 obtains the verification voltage value according to the comparison table, and reads the latest version of the data according to the read voltage.

相似地,選擇性地重複執行步驟S410~步驟S440,第2圖之區塊200寫入資料順序以下述資料順序為例:第二資料B1、第二資料B2、第三資料C1、第一資料A3、第一資料A4、第二資料B3、第二資料B4。 Similarly, selectively repeating steps S410 to S440, the sequence of writing data in the block 200 of FIG. 2 takes the following data sequence as an example: second data B1, second data B2, third data C1, first data A3, first data A4, second data B3, second data B4.

當第二資料B1準備被寫入至區塊200時,控制器110以重寫指令RW1控制字元線WL2將第二資料B1 寫入頁面220,其中第二資料B1為第一版本。 When the second data B1 is ready to be written to the block 200, the controller 110 controls the word line WL2 to rewrite the second data B1 with a rewrite command RW1 Write to page 220, where the second data B1 is the first version.

另一方面,請參照第3B圖。第3B圖係根據本案之一些實施例所繪示於編程資料至第2圖之區塊200中的頁面220的臨界電壓與記憶胞數量之示意圖。在記憶胞被寫入資料之前的邏輯值如階段RW0所示,此時的記憶胞為抹除狀態。在一實施例中,記憶胞的邏輯值被設定為第一邏輯值,例如1。在第二資料B1被寫入頁面220時,如第3B圖所示,對應至重寫指令RW1的臨界電壓新增至電壓Vp11。電壓Vp11之前的一電壓範圍的記憶胞的邏輯值設為第一邏輯值,例如1。電壓Vp11之後的一電壓範圍的記憶胞的邏輯值設為第二邏輯值,例如0。控制器110會記錄頁面220的重寫次數為1次。 On the other hand, please refer to Figure 3B. FIG. 3B is a schematic diagram showing the threshold voltage and the number of memory cells of the page 220 in the programming data to the block 200 of FIG. 2 according to some embodiments of the present case. The logic value before the memory cell is written with data is shown in stage RW0, and the memory cell at this time is in the erasing state. In one embodiment, the logic value of the memory cell is set to the first logic value, for example 1. When the second data B1 is written to the page 220, as shown in FIG. 3B, the threshold voltage corresponding to the rewrite command RW1 is added to the voltage Vp11. The logic value of the memory cell in a voltage range before the voltage Vp11 is set as the first logic value, for example, 1. The logic value of the memory cell in a voltage range after the voltage Vp11 is set as the second logic value, for example, 0. The controller 110 records that the number of times of rewriting the page 220 is one.

在控制器110讀取資料時,只需判斷兩種電壓狀態即可讀取到最新版本的資料。舉例來說,在欲讀取第二資料B1時,控制器110只需控制以(如第3B圖所示)讀取電壓Vr1之電壓即可讀到正確的資料。第二資料B1被更新及被讀取的程序相似於第3A圖的說明而不予重述。 When the controller 110 reads the data, it only needs to judge the two voltage states to read the latest version of the data. For example, when the second data B1 is to be read, the controller 110 only needs to control (as shown in FIG. 3B) to read the voltage Vr1 to read the correct data. The procedure for updating and reading the second data B1 is similar to the description in FIG. 3A and will not be repeated.

當第三資料C1準備被寫入至區塊200時,控制器110以重寫指令RW1控制字元線WL3將第三資料C1寫入頁面230,其中第三資料C1為第一版本。 When the third data C1 is ready to be written to the block 200, the controller 110 controls the word line WL3 to write the third data C1 to the page 230 with the rewrite instruction RW1, wherein the third data C1 is the first version.

另一方面,請參照第3C圖。第3C圖係根據本案之一些實施例所繪示於編程資料至第2圖之區塊200中的頁面230的臨界電壓與記憶胞數量之示意圖。在記 憶胞被寫入資料之前的邏輯值如階段RW0所示,此時的記憶胞為抹除狀態。在一實施例中,記憶胞的邏輯值被設定為第一邏輯值,例如1。在第三資料C1被寫入頁面220時,如第3C圖所示,對應至重寫指令RW1的臨界電壓新增至電壓Vp21。電壓Vp21之前的一電壓範圍的記憶胞的邏輯值設為第一邏輯值,例如1。電壓Vp21之後的一電壓範圍的記憶胞的邏輯值設為第二邏輯值,例如0。控制器110會記錄頁面230的重寫次數為1次。 On the other hand, please refer to Figure 3C. FIG. 3C is a schematic diagram showing the threshold voltage and the number of memory cells of the page 230 in the programming data to the block 200 in FIG. 2 according to some embodiments of the present invention. In mind The logic value before the memory cell is written into the data is shown in stage RW0, at this time the memory cell is in the erased state. In one embodiment, the logic value of the memory cell is set to the first logic value, for example 1. When the third data C1 is written to the page 220, as shown in FIG. 3C, the threshold voltage corresponding to the rewrite command RW1 is added to the voltage Vp21. The logic value of the memory cell in a voltage range before the voltage Vp21 is set as the first logic value, for example, 1. The logical value of the memory cell in a voltage range after the voltage Vp21 is set as the second logical value, for example, 0. The controller 110 records that the number of times of rewriting the page 230 is one.

在控制器110讀取資料時,只需判斷兩種電壓狀態即可讀取到最新版本的資料。舉例來說,在欲讀取第三資料C1時,控制器110只需控制以(如第3C圖所示)讀取電壓Vr1之電壓即可讀到正確的資料。 When the controller 110 reads the data, it only needs to judge the two voltage states to read the latest version of the data. For example, when the third data C1 is to be read, the controller 110 only needs to control (as shown in FIG. 3C) to read the voltage Vr1 to read the correct data.

在傳統的增量階躍脈衝程式(Incremental Step Pulse Programming,ISPP)的編程方法中,以四級單元架構的記憶體晶片為例,每個記憶胞只能被編程四次。當寫入資料是熱資料時,由於熱資料僅佔記憶體中的整體資料量的少部分,但性質上為需要經常被更新,因此傳統的編程方法中,儲存熱資料的記憶胞在執行了四次的更新之後便無法再繼續編程資料,導致記憶體晶片整體的使用效率低落。相較之下,本案的操作於快閃記憶體晶片150之重新寫入方法可讓儲存熱資料的記憶胞更新次數提升至最多15次,提高了記憶胞的寫入效率。據此,相較於傳統的編程方法,本案可以在多級單元架構的記憶體晶片中提升資料寫入效率的有益功效。 In the traditional incremental step pulse programming (ISPP) programming method, taking a memory chip with a four-level cell architecture as an example, each memory cell can only be programmed four times. When the written data is hot data, because the hot data only occupies a small part of the total amount of data in the memory, but the nature needs to be updated frequently, so in the traditional programming method, the memory cell that stores the hot data is executed. After four updates, the programming data can no longer be continued, resulting in inefficient use of the entire memory chip. In contrast, the method of rewriting the flash memory chip 150 in this case can increase the number of memory cell updates that store hot data to a maximum of 15 times, which improves the writing efficiency of the memory cell. According to this, compared with the traditional programming method, this case can improve the beneficial effect of data writing efficiency in the memory chip of the multi-level cell structure.

另一方面,由於每一個記憶胞可重新寫入的次數增加,因此在記憶體區塊的抹寫次數(program/erase cycle)相同的情況下,本案可提升記憶胞的總寫入位元組(Total Byte Written)。此外,在總寫入位元組相同的情況下,本案可以讓記憶體區塊的抹寫次數降低,如此一來可降低在記憶體晶片中使用的錯誤更正碼的強度,以減少處理錯誤更正碼所需的花費。 On the other hand, since the number of rewritable times per memory cell increases, in the case of the same program/erase cycle of the memory block, this case can increase the total write bytes of the memory cell (Total Byte Written). In addition, in the case that the total written bytes are the same, this case can reduce the number of erasures of the memory block, which can reduce the strength of the error correction code used in the memory chip to reduce the processing of error correction The cost of the code.

以及,本揭示文件的操作於快閃記憶體晶片150之重新寫入方法提供在資料更新時不需立即抹除舊資料,而是在區塊中的無效資料比例高於一定門檻值時,才抹除整個區塊。如此一來,可以避免特定頁面的資料更新比例過於頻繁,所造成的頁面損耗問題。 And, the rewriting method of the disclosed document operating on the flash memory chip 150 provides that it is not necessary to erase the old data immediately when the data is updated, but only when the proportion of invalid data in the block is above a certain threshold. Erase the entire block. In this way, the problem of page loss caused by too frequent updating of data on a specific page can be avoided.

此外,在控制器110讀取資料時,只需判斷兩種電壓狀態即可讀取到最新版本的資料。相較於傳統之多級單元架構中,控制器110需要記錄4個或以上的驗證電壓,才能正確地讀到每個電壓範圍對應的資料,對於電壓控制稍有不慎,則會讀取到錯誤的資料。本揭示文件運用了多級單元的架構來儲存同一筆資料之更新內容,頁面中一次儲存一筆資料,但可在頁面中使用多次的更新,如此一來,可降低資料讀取及寫入資料時的複雜度。 In addition, when the controller 110 reads the data, it only needs to judge the two voltage states to read the latest version of the data. Compared with the traditional multi-level cell architecture, the controller 110 needs to record 4 or more verification voltages in order to correctly read the data corresponding to each voltage range. If you are careless about voltage control, you will read Wrong information. This disclosure uses a multi-level unit structure to store the updated content of the same data. One page of data is stored at a time, but multiple updates can be used in the page. In this way, data reading and writing can be reduced Time complexity.

請參照第5圖,其係根據本案之一些實施例所繪示之執行記憶體回收之步驟流程圖。請一併參照第1圖、第2圖及第5圖以得到清楚的理解。 Please refer to FIG. 5, which is a flowchart of steps for performing memory recovery according to some embodiments of the present case. Please refer to Figure 1, Figure 2 and Figure 5 for a clear understanding.

在步驟S510中,控制器110使用區塊200,並且記憶體回收器133計算區塊200中的無效空間大小。 In step S510, the controller 110 uses the block 200, and the memory recycler 133 calculates the size of the invalid space in the block 200.

舉例來說,以區塊200包含三個頁面210、220、230,並且各頁面包含一個記憶單元為例。若記憶單元為可以運行於四級單元(QLC)之架構,則在每次儲存一個位元的情況下,依據前述第4圖之步驟S410~步驟S440,一個頁面最多可以執行重新寫入15次,因此,總空間大小為45(15*3)。另一方面,在第2圖之區塊200中,有效資料為第一資料A4、第二資料B4、以及第三資料C1,因此,無效空間大小為6(即前述被標記為無效資料之第一資料A1、A2、A3及第二資料B1、B2、B3)。 For example, suppose block 200 includes three pages 210, 220, and 230, and each page includes a memory unit. If the memory cell is a four-level cell (QLC) architecture, each time a bit is stored, a page can be rewritten up to 15 times according to steps S410 to S440 in the aforementioned Figure 4 , Therefore, the total space size is 45 (15*3). On the other hand, in the block 200 of FIG. 2, the valid data is the first data A4, the second data B4, and the third data C1, so the invalid space size is 6 (that is, the aforementioned One data A1, A2, A3 and second data B1, B2, B3).

值得一提的是,記憶體技術裝置層140中的可重寫區塊表會記錄區塊的重寫計數(rewrite count)。舉例來說,第2圖所示之區塊200已寫入9次資料,因此在可重寫區塊表中記錄區塊200的重寫計數為9。在一些實施例中,區塊200的重寫計數可以為但不限於頁面210、頁面220、及頁面230的重寫次數之總和。 It is worth mentioning that the rewritable block table in the memory technology device layer 140 records the rewrite count of blocks. For example, the block 200 shown in FIG. 2 has written data 9 times, so the rewrite count of the block 200 is recorded in the rewritable block table as 9. In some embodiments, the rewrite count of block 200 may be, but not limited to, the sum of the rewrite times of page 210, page 220, and page 230.

在步驟S520中,控制器110判斷區塊200中無效空間大小佔總空間大小之比例是否大於效用臨界值(efficiency threshold)。 In step S520, the controller 110 determines whether the ratio of the size of the invalid space in the block 200 to the size of the total space is greater than the efficiency threshold.

如第2圖所示之區塊200的實施例中,無效空間大小佔總空間大小之比例約為13%,代表區塊200的剩餘可用次數還很充裕,而可繼續使用區塊200。值得一提的是,本揭示文件不限制效用臨界值之實際數值,可 依據實際狀況而作對應的數值設定,例如效用臨界值設定為95%,代表讓區塊200的使用次數較高。在另一些實施例中,控制器110設定區塊200的每個頁面的可重寫次數為7次,則總空間大小為21。如第2圖所示之區塊200的儲存狀態(共6筆無效資料),因此,無效空間大小佔總空間大小之比例約為29%。換言之,各頁面的重寫次數的設定可決定區塊被重寫的上限次數。 As shown in FIG. 2 in the embodiment of block 200, the ratio of the invalid space size to the total space size is about 13%, which means that the remaining available times of the block 200 are still sufficient, and the block 200 can continue to be used. It is worth mentioning that this disclosure does not limit the actual value of the utility threshold. Corresponding numerical settings are made according to the actual situation, for example, the utility threshold is set to 95%, which means that the block 200 is used more frequently. In other embodiments, the controller 110 sets the number of rewritable times of each page of the block 200 to 7 times, and the total space size is 21. As shown in the storage status of the block 200 shown in FIG. 2 (a total of 6 invalid data), the ratio of invalid space to the total space is about 29%. In other words, the setting of the number of times of rewriting of each page can determine the upper limit of the number of times the block is rewritten.

若在步驟S520中,無效空間大小占總空間大小之比例不大於效用臨界值,則回到步驟S510。若無效空間大小占總空間大小之比例大於效用臨界值,則執行步驟S530。 If in step S520, the ratio of the invalid space size to the total space size is not greater than the utility threshold, then return to step S510. If the ratio of the invalid space size to the total space size is greater than the utility threshold, step S530 is executed.

在步驟S530中,控制器110編程區塊200中的有效之資料至另一區塊(第2圖未繪示)。 In step S530, the controller 110 programs the valid data in the block 200 to another block (not shown in FIG. 2).

舉例來說,區塊200之有效資料為第一資料A4、第二資料B4、第三資料C1。因此,將此些有效資料寫入至另一空白之區塊。 For example, the valid data of the block 200 are the first data A4, the second data B4, and the third data C1. Therefore, this valid data is written to another blank block.

接著,在步驟S540中,控制器110標記區塊200為無效之區塊。因此,控制器110將不再讀取區塊200中的資料,以及不再將資料寫入區塊200。在一些實施例中,於區塊200的空間需要被使用時,才抹除區塊200中的資料。 Next, in step S540, the controller 110 marks the block 200 as an invalid block. Therefore, the controller 110 will no longer read the data in the block 200 and no longer write the data in the block 200. In some embodiments, the data in the block 200 is erased only when the space of the block 200 needs to be used.

請參照第6圖,其係根據本案之一些實施例所繪示之編程干擾偵測之步驟流程圖。請一併參照第1圖、第2圖及第6圖以得到清楚的理解。 Please refer to FIG. 6, which is a flowchart of steps of program interference detection according to some embodiments of the present case. Please refer to Figure 1, Figure 2 and Figure 6 together for a clear understanding.

在步驟S610中,控制器110編程一資料至區塊200之一頁面。舉例來說,將第二資料B1寫入頁面220中,此步驟之已詳細說明如前述。 In step S610, the controller 110 programs a data to a page of the block 200. For example, the second data B1 is written into the page 220. The detailed description of this step is as described above.

接著,在步驟S620中,干擾處理器135遞增區塊200中與執行資料編程之頁面相鄰之其他頁面(例如頁面210及頁面230)之干擾係數(disturb factor),並重置執行資料編程之頁面之干擾係數。 Next, in step S620, the interference processor 135 increments the disturb factor of other pages (such as page 210 and page 230) adjacent to the page performing data programming in the block 200, and resets the performance factor The interference factor of the page.

舉例來說,以區塊200中已儲存有第一資料A1為例,頁面220與頁面230中尚未被寫入任何資料。此時,頁面210的干擾係數被重置為0,頁面220的干擾係數從0被遞增至1(以所有空白頁面的干擾係數之初使值是0為例)。若第一資料A2接續被寫入頁面210時,頁面210的干擾係數被重置為0,頁面220的干擾係數從1被遞增至2。 For example, taking the first data A1 already stored in the block 200 as an example, no data has been written in the pages 220 and 230. At this time, the interference coefficient of page 210 is reset to 0, and the interference coefficient of page 220 is incremented from 0 to 1 (taking the initial value of the interference coefficient of all blank pages as 0). If the first data A2 is continuously written to the page 210, the interference coefficient of the page 210 is reset to 0, and the interference coefficient of the page 220 is increased from 1 to 2.

接著,當第二資料B1被寫入頁面220時,與頁面220相鄰之頁面210與頁面230之干擾係數會分別會從0遞增至1。並且,頁面220的干擾係數會被重置為0。以此類推,在寫入資料順序為<A1,A2,B1,B2,C1,A3,A4,B3,B4>的實施例中,頁面210的干擾係數為2,頁面220的干擾係數為0,頁面230的干擾係數為2。 Then, when the second data B1 is written to the page 220, the interference coefficients of the pages 210 and 230 adjacent to the page 220 will increase from 0 to 1, respectively. Moreover, the interference coefficient of page 220 will be reset to zero. By analogy, in the embodiment where the order of writing data is <A1, A2, B1, B2, C1, A3, A4, B3, B4>, the interference coefficient of page 210 is 2 and the interference coefficient of page 220 is 0. The interference factor of page 230 is 2.

在步驟S630中,判斷區塊200中各頁面的干擾係數是否大於一干擾臨界值(disturb threshold)。 In step S630, it is determined whether the interference coefficient of each page in the block 200 is greater than a disturbance threshold (disturb threshold).

以干擾臨界值被設定成1為例,頁面210與頁面230的干擾係數均大於干擾臨界值。 Taking the interference threshold set to 1 as an example, the interference coefficients of pages 210 and 230 are both greater than the interference threshold.

接著,在步驟S640中,當頁面的干擾係數大於干擾臨界值時,重新編程資料至該頁面,以重置該頁面的干擾係數。 Next, in step S640, when the interference coefficient of the page is greater than the interference threshold, reprogram the data to the page to reset the interference coefficient of the page.

舉例來說,如第2圖所示,頁面210與頁面230的干擾係數均大於干擾臨界值,此時,第一資料A4會被重新編程至頁面210,以重置頁面210的干擾係數。相似地,第三資料C1會被重新編程至頁面230,以重置頁面230的干擾係數。 For example, as shown in FIG. 2, the interference coefficients of page 210 and page 230 are greater than the interference threshold. At this time, the first data A4 will be reprogrammed to page 210 to reset the interference coefficient of page 210. Similarly, the third data C1 will be reprogrammed to the page 230 to reset the interference factor of the page 230.

另一方面,在當頁面的干擾係數大於干擾臨界值時,亦可執行步驟S650。在步驟S650中,當頁面的干擾係數大於干擾臨界值時,重新編程資料至另一頁面,並標記干擾係數大於干擾臨界值之頁面為無效之頁面。 On the other hand, when the interference coefficient of the page is greater than the interference threshold, step S650 may also be executed. In step S650, when the interference coefficient of the page is greater than the interference threshold, reprogram the data to another page, and mark the page with the interference coefficient greater than the interference threshold as an invalid page.

舉例來說,如第2圖所示,頁面210儲存第一資料A4以及頁面230儲存第三資料C1。當頁面210的干擾係數大於干擾臨界值時,第一資料A4會被重新寫入至另一空白頁面(第2圖未繪示),並且頁面210會被標記為無效之頁面。相似地,當頁面230的干擾係數大於干擾臨界值時,第三資料C1會被寫入至又另一空白頁面(第2圖未繪示),並且頁面230會被標記為無效之頁面。 For example, as shown in FIG. 2, the page 210 stores the first data A4 and the page 230 stores the third data C1. When the interference coefficient of the page 210 is greater than the interference threshold, the first data A4 will be rewritten to another blank page (not shown in FIG. 2), and the page 210 will be marked as an invalid page. Similarly, when the interference factor of the page 230 is greater than the interference threshold, the third data C1 will be written to another blank page (not shown in FIG. 2), and the page 230 will be marked as an invalid page.

值得一提的是,在步驟S630中判斷頁面的干擾係數大於干擾臨界值時,可選擇性地執行步驟S640或步驟S650。步驟S640及步驟S650均可處理頁面被干擾程度過高的問題。 It is worth mentioning that, when it is determined in step S630 that the interference coefficient of the page is greater than the interference threshold, step S640 or step S650 may be selectively performed. Both steps S640 and S650 can deal with the problem that the page is too disturbed.

請復參照步驟S630,於頁面220的干擾係數小於干擾臨界值時,則回到步驟S610,繼續使用該頁面。 Please refer back to step S630. When the interference coefficient of the page 220 is less than the interference threshold, return to step S610 to continue using the page.

在一些實施例中,本揭示文件提出一種非暫態電腦可讀取記錄媒體,可儲存多個程式碼。程式碼被載入至如第1圖之控制器110後,控制器110執行程式碼並執行包含第4圖、第5圖及第6圖之步驟。舉例來說,控制器110接收資料並根據資料之版本將該資料儲存於對應之頁面、增加電壓視窗至臨界電壓以作為寫入資料的電壓、標記前一版本的資料為無效並標記新版本的資料為有效、以及記錄各頁面經歷重寫的次數。 In some embodiments, the present disclosure proposes a non-transitory computer-readable recording medium that can store multiple program codes. After the program code is loaded into the controller 110 as shown in FIG. 1, the controller 110 executes the program code and performs the steps including FIG. 4, FIG. 5, and FIG. 6. For example, the controller 110 receives the data and stores the data in the corresponding page according to the version of the data, increases the voltage window to a critical voltage as the voltage for writing the data, marks the previous version of the data as invalid and marks the new version The information is valid and records the number of times each page has been rewritten.

本揭示文件的操作於快閃記憶體晶片150之編程干擾偵測方法偵測相鄰頁面之間的干擾偵測,避免同一個資料在同一個頁面頻繁地被使用所造成之影響,以維護其他頁面的資料正確性。 This disclosed document operates on the flash memory chip 150 programming interference detection method to detect interference detection between adjacent pages to avoid the impact of frequent use of the same data on the same page to maintain other The accuracy of the information on the page.

綜上所述,本揭示文件之記憶體管理系統及記憶體操作方法考量到經常使用資料與不常使用資料在記憶體晶片中的區分不同的儲存方式。對於經常使用資料在同一頁面以遞增的臨界電壓來編程資料,據以降低對區塊的抹除頻率,提升可用度。本揭示文件之記憶體回收及干擾偵測方法對記憶體晶片的寫入方式進行管理,例如以最少的抹除次數來回收記憶體,以及維護記憶體資料的正確性。據此,記憶體晶片的讀取、編程、及抹除方面均可延長記憶體晶片的使用壽命。 In summary, the memory management system and memory operation method of the disclosed document consider different storage methods for frequently used data and infrequently used data in the memory chip. For frequently used data to program data with increasing threshold voltage on the same page, the frequency of erasing blocks is reduced, and the availability is improved. The memory recovery and interference detection method of the disclosed document manages the writing method of the memory chip, such as recovering the memory with the minimum number of erasures, and maintaining the accuracy of the memory data. Accordingly, the reading, programming, and erasing of the memory chip can extend the service life of the memory chip.

另外,上述例示包含依序的示範步驟,但該 些步驟不必依所顯示的順序被執行。以不同順序執行該些步驟皆在本揭示內容的考量範圍內。在本揭示內容之實施例的精神與範圍內,可視情況增加、取代、變更順序及/或省略該些步驟。 In addition, the above example includes sequential exemplary steps, but the These steps do not have to be performed in the order shown. Performing these steps in different orders is within the scope of this disclosure. Within the spirit and scope of the embodiments of the present disclosure, the order may be added, replaced, changed, and/or omitted as appropriate.

雖然本案已以實施方式揭示如上,然其並非用以限定本案,任何熟習此技藝者,在不脫離本案之精神和範圍內,當可作各種之更動與潤飾,因此本案之保護範圍當視後附之申請專利範圍所界定者為準。 Although this case has been disclosed as above by way of implementation, it is not intended to limit this case. Anyone who is familiar with this skill can make various changes and modifications within the spirit and scope of this case, so the scope of protection of this case should be considered The scope of the attached patent application shall prevail.

100‧‧‧記憶體系統 100‧‧‧Memory system

110‧‧‧控制器 110‧‧‧Controller

120‧‧‧檔案系統 120‧‧‧File System

130‧‧‧快閃記憶體轉換層 130‧‧‧Flash memory conversion layer

131‧‧‧寫入資料頻率分析器 131‧‧‧ Write data frequency analyzer

133‧‧‧記憶體回收器 133‧‧‧Memory Recycler

135‧‧‧干擾處理器 135‧‧‧ interference processor

140‧‧‧記憶體技術裝置層 140‧‧‧Memory technology device layer

141‧‧‧編程程序 141‧‧‧program

143‧‧‧讀取程序 143‧‧‧Reading program

145‧‧‧抹除程序 145‧‧‧Erase procedure

150‧‧‧快閃記憶體晶片 150‧‧‧Flash memory chip

151‧‧‧一般區塊範圍 151‧‧‧General block range

153‧‧‧可重寫區塊範圍 153‧‧‧ rewritable block range

Claims (10)

一種記憶體系統,包含:一快閃記憶體晶片;以及一控制器,耦接該快閃記憶體晶片,其中該控制器經配置以:自一檔案系統接收一第一版本之一第一資料,以儲存該第一版本之該第一資料至該快閃記憶體晶片之一第一頁面;以及響應於該第一資料之一第二版本以編程該第二版本之該第一資料於該第一頁面,其中該第二版本新於該第一版本。 A memory system includes: a flash memory chip; and a controller coupled to the flash memory chip, wherein the controller is configured to: receive a first version of a first data from a file system To store the first data of the first version to a first page of the flash memory chip; and in response to a second version of the first data to program the first data of the second version in the The first page, where the second version is newer than the first version. 如請求項1所述之記憶體系統,其中當該控制器編程該第二版本之該第一資料於該第一頁面時,該控制器還用以:增加一電壓視窗至一臨界電壓;以及標記該第一版本的該第一資料為一無效資料以及標記該第二版本的該第一資料為一有效資料,並於一可重寫區塊表中遞增對應該第一頁面所在的一第一區塊的一重寫計數。 The memory system of claim 1, wherein when the controller programs the second version of the first data on the first page, the controller is further used to: increase a voltage window to a threshold voltage; and Mark the first data of the first version as an invalid data and mark the first data of the second version as a valid data, and increment the first data corresponding to the first page in a rewritable block table One rewrite count for one block. 如請求項2所述之記憶體系統,其中該控制器還用以根據該重寫計數計算該第一區塊中的一無效空間大小,以及該控制器於判斷該第一區 塊之該無效空間佔該第一區塊的一總空間大小之一比例大於一效用臨界值時,編程該第一區塊中有效之該第一資料至該快閃記憶體晶片之一第二區塊,並標記該第一區塊為該無效資料。 The memory system of claim 2, wherein the controller is further used to calculate an invalid space size in the first block according to the rewrite count, and the controller determines the first area When the ratio of the invalid space of the block to a total space of the first block is greater than a utility threshold, the first data that is valid in the first block is programmed to a second of the flash memory chip Block, and mark the first block as the invalid data. 如請求項1所述之記憶體系統,其中當該控制器編程一第二資料至一第一區塊之一第二頁面時,該控制器還用以遞增該第一區塊之一第一頁面之一干擾係數,並於該第一頁面之該干擾係數大於一干擾臨界值時,該控制器還用以重新編程該第一資料至該第一頁面以重置該第一頁面之該干擾係數。 The memory system of claim 1, wherein when the controller programs a second data to a second page of a first block, the controller is also used to increment a first of the first block An interference coefficient of a page, and when the interference coefficient of the first page is greater than an interference threshold, the controller is also used to reprogram the first data to the first page to reset the interference of the first page coefficient. 如請求項1所述之記憶體系統,其中當該控制器編程一第二資料至一第一區塊之一第二頁面時,該控制器還用以遞增第一區塊之一第一頁面之一干擾係數,並於該第一頁面之該干擾係數大於一干擾臨界值時,該控制器還用以重新編程該第一資料至該第一區塊之一第三頁面,並標記該第一頁面為一無效資料。 The memory system of claim 1, wherein when the controller programs a second data to a second page of a first block, the controller is also used to increment a first page of the first block An interference coefficient, and when the interference coefficient of the first page is greater than an interference threshold, the controller is also used to reprogram the first data to a third page of the first block and mark the first One page is invalid data. 一種記憶體操作方法,包含:自一檔案系統接收一第一版本之一第一資料,以透過一控制器儲存該第一版本之該第一資料至一 快閃記憶體晶片之一第一頁面;以及響應於該第一資料之一第二版本,透過該控制器編程該第二版本之該第一資料於該第一頁面,其中該第二版本新於該第一版本。 A memory operation method includes: receiving a first data of a first version from a file system to store the first data of the first version to a through a controller A first page of a flash memory chip; and in response to a second version of the first data, programming the second version of the first data on the first page through the controller, wherein the second version is new For the first version. 如請求項6所述之記憶體操作方法,其中編程該第二版本之該第一資料於該第一頁面還包含:增加一電壓視窗至一臨界電壓;以及標記該第一版本的該第一資料為一無效資料,以及標記該第二版本的該第一資料為一有效資料,並於一可重寫區塊表中遞增對應該第一頁面所在的一第一區塊的一重寫計數。 The memory operation method according to claim 6, wherein programming the first data of the second version on the first page further comprises: adding a voltage window to a threshold voltage; and marking the first version of the first version The data is an invalid data, and the first data of the second version is marked as a valid data, and a rewrite count corresponding to a first block where the first page is located is incremented in a rewritable block table . 如請求項7所述之記憶體操作方法,還包含:根據該重寫計數計算該第一區塊中的一無效空間;以及於判斷該第一區塊之該無效空間佔該第一區塊的一總空間大小之一比例大於一效用臨界值時,編程該第一區塊中有效之該第一資料至該快閃記憶體晶片之一第二區塊,並標記該第一區塊為該無效資料。 The memory operation method according to claim 7, further comprising: calculating an invalid space in the first block according to the rewrite count; and determining that the invalid space of the first block occupies the first block When a proportion of a total space size is greater than a utility threshold, program the first data valid in the first block to a second block of the flash memory chip, and mark the first block as The invalid data. 如請求項6所述之記憶體操作方法,還包含:當一第二資料被編程至一第一區塊之一第二頁面時,遞增該第一區塊之一第一頁面之一干擾係數,並於該第一頁面之該干擾係數大於一干擾臨界值時,重新編程該第一資料至該第一頁面以重置該第一頁面之該干擾係數。 The memory operation method according to claim 6, further comprising: when a second data is programmed to a second page of a first block, incrementing an interference coefficient of a first page of the first block , And when the interference coefficient of the first page is greater than an interference threshold, reprogram the first data to the first page to reset the interference coefficient of the first page. 如請求項6所述之記憶體操作方法,還包含:當一第二資料被編程至一第一區塊之一第二頁面時,遞增該第一區塊之一第一頁面之一干擾係數,並於該第一頁面之該干擾係數大於一干擾臨界值時,重新編程該第一資料至該第一區塊之一第三頁面;以及標記該第一頁面為一無效資料。 The memory operation method according to claim 6, further comprising: when a second data is programmed to a second page of a first block, incrementing an interference coefficient of a first page of the first block , And when the interference coefficient of the first page is greater than an interference threshold, reprogram the first data to a third page of the first block; and mark the first page as an invalid data.
TW108133277A 2019-09-16 2019-09-16 Memory system and method of operating memory TWI694449B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW108133277A TWI694449B (en) 2019-09-16 2019-09-16 Memory system and method of operating memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW108133277A TWI694449B (en) 2019-09-16 2019-09-16 Memory system and method of operating memory

Publications (2)

Publication Number Publication Date
TWI694449B true TWI694449B (en) 2020-05-21
TW202113850A TW202113850A (en) 2021-04-01

Family

ID=71896249

Family Applications (1)

Application Number Title Priority Date Filing Date
TW108133277A TWI694449B (en) 2019-09-16 2019-09-16 Memory system and method of operating memory

Country Status (1)

Country Link
TW (1) TWI694449B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI718975B (en) * 2020-07-17 2021-02-11 汎思數據股份有限公司 Method and device for increasing read/write speed of memory data

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI270076B (en) * 2002-05-14 2007-01-01 Taiwan Semiconductor Mfg Flash memory cell array structure featuring selectable bit data modification
US7516283B2 (en) * 2004-05-07 2009-04-07 Pioneer Corporation Memory control device, in-car device, memory control method, and computer product for managing data in response to various power states
TW201211764A (en) * 2010-04-15 2012-03-16 Univ Ramot Multiple programming of flash memory without erase
US20160210070A1 (en) * 2015-01-16 2016-07-21 Renesas Electronics Corporation Information processing apparatus and flash memory control method
TWI545587B (en) * 2010-08-06 2016-08-11 半導體能源研究所股份有限公司 Semiconductor device and method for driving semiconductor device
TWI608352B (en) * 2016-07-10 2017-12-11 華邦電子股份有限公司 Method for data management and device having a flash memory

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI270076B (en) * 2002-05-14 2007-01-01 Taiwan Semiconductor Mfg Flash memory cell array structure featuring selectable bit data modification
US7516283B2 (en) * 2004-05-07 2009-04-07 Pioneer Corporation Memory control device, in-car device, memory control method, and computer product for managing data in response to various power states
TW201211764A (en) * 2010-04-15 2012-03-16 Univ Ramot Multiple programming of flash memory without erase
TWI545587B (en) * 2010-08-06 2016-08-11 半導體能源研究所股份有限公司 Semiconductor device and method for driving semiconductor device
US20160210070A1 (en) * 2015-01-16 2016-07-21 Renesas Electronics Corporation Information processing apparatus and flash memory control method
TWI608352B (en) * 2016-07-10 2017-12-11 華邦電子股份有限公司 Method for data management and device having a flash memory

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI718975B (en) * 2020-07-17 2021-02-11 汎思數據股份有限公司 Method and device for increasing read/write speed of memory data

Also Published As

Publication number Publication date
TW202113850A (en) 2021-04-01

Similar Documents

Publication Publication Date Title
US9019770B2 (en) Data reading method, and control circuit, memory module and memory storage apparatus and memory module using the same
US8386860B2 (en) Methods of calculating compensation voltage and adjusting threshold voltage and memory apparatus and controller
US9703698B2 (en) Data writing method, memory controller and memory storage apparatus
TWI623878B (en) Data reading method and storage controller
TWI545572B (en) Memory cell programming method, memory control circuit unit and memory storage apparatus
US20100131809A1 (en) Apparatus and methods for generating row-specific reading thresholds in flash memory
US9478298B2 (en) Memory system and method of reading data thereof
US8972653B2 (en) Memory management method, and memory controller and memory storage apparatus using the same
US20120206966A1 (en) Method for modifying data more than once in a multi-level cell memory location within a memory array
TWI479314B (en) Method of storing system data, and memory controller and memory storage apparatus using the same
US20150262677A1 (en) Data storing method, memory control circuit unit and memory storage apparatus
TWI536386B (en) Memory programming method, memory controlling circuit unit and memory storage
US11663068B2 (en) Write abort error detection in multi-pass programming
TWI509615B (en) Data storing method, and memory controller and memory storage apparatus using the same
TW201351137A (en) Memory management method, memory controller and memory storage device using the same
US10712970B2 (en) Flash memory controller and associated accessing method and electronic device
TWI694449B (en) Memory system and method of operating memory
TWI574272B (en) Erase operation setting method, memory controlling circuit unit and memory storage device
CN114520015A (en) Time-based combining of block families of memory devices
US20240071440A1 (en) Determining read voltage offset in memory devices
US11630726B2 (en) Memory system and operating method thereof
US11709727B2 (en) Managing error-handling flows in memory devices
US11216208B1 (en) Memory system, memory controller, and operation method of memory system
US11159176B1 (en) Data-assisted LDPC decoding
CN105761754B (en) Memory cell programming method, memory control circuit unit and memory device