IT1251623B - Dispositivo di memoria a semiconduttore - Google Patents

Dispositivo di memoria a semiconduttore

Info

Publication number
IT1251623B
IT1251623B ITMI912808A ITMI912808A IT1251623B IT 1251623 B IT1251623 B IT 1251623B IT MI912808 A ITMI912808 A IT MI912808A IT MI912808 A ITMI912808 A IT MI912808A IT 1251623 B IT1251623 B IT 1251623B
Authority
IT
Italy
Prior art keywords
memory device
semiconductor memory
bit lines
leakage current
complementary bit
Prior art date
Application number
ITMI912808A
Other languages
English (en)
Inventor
Changrae Kin
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of ITMI912808A0 publication Critical patent/ITMI912808A0/it
Publication of ITMI912808A1 publication Critical patent/ITMI912808A1/it
Application granted granted Critical
Publication of IT1251623B publication Critical patent/IT1251623B/it

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
  • Semiconductor Memories (AREA)
  • Dram (AREA)

Abstract

Un dispositivo di memoria a semiconduttore comprende un circuito di compensazione di corrente di dispersione per linee di bit complementari per impedire un'errata operazione di lettura o di scrittura in una memoria statica ad accesso casuale ad alta densità. Sono previsti transistor MOS con un gate interconnesso e terminali di scarico per controllare la compensazione della corrente di dispersione alle linee di bit complementari.
ITMI912808A 1991-05-28 1991-10-23 Dispositivo di memoria a semiconduttore IT1251623B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910008735A KR920022301A (ko) 1991-05-28 1991-05-28 반도체 기억장치

Publications (3)

Publication Number Publication Date
ITMI912808A0 ITMI912808A0 (it) 1991-10-23
ITMI912808A1 ITMI912808A1 (it) 1993-04-23
IT1251623B true IT1251623B (it) 1995-05-17

Family

ID=19315060

Family Applications (1)

Application Number Title Priority Date Filing Date
ITMI912808A IT1251623B (it) 1991-05-28 1991-10-23 Dispositivo di memoria a semiconduttore

Country Status (7)

Country Link
KR (1) KR920022301A (it)
CN (1) CN1067325A (it)
DE (1) DE4135686A1 (it)
FR (1) FR2677162A1 (it)
GB (1) GB2256297A (it)
IT (1) IT1251623B (it)
NL (1) NL9101772A (it)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5828610A (en) * 1997-03-31 1998-10-27 Seiko Epson Corporation Low power memory including selective precharge circuit
JP3544933B2 (ja) * 2000-10-05 2004-07-21 Ｎｅｃエレクトロニクス株式会社 半導体集積回路
US6608786B2 (en) * 2001-03-30 2003-08-19 Intel Corporation Apparatus and method for a memory storage cell leakage cancellation scheme
KR100732390B1 (ko) * 2001-12-29 2007-06-27 매그나칩 반도체 유한회사 전류 미러형 누설 전류 보상 회로
JP4251815B2 (ja) * 2002-04-04 2009-04-08 株式会社ルネサステクノロジ 半導体記憶装置
JP3904499B2 (ja) * 2002-09-25 2007-04-11 松下電器産業株式会社 半導体記憶装置
JP2004152092A (ja) * 2002-10-31 2004-05-27 Matsushita Electric Ind Co Ltd 電圧源回路
DE10255102B3 (de) * 2002-11-26 2004-04-29 Infineon Technologies Ag SRAM-Speicherzelle mit Mitteln zur Erzielung eines vom Speicherzustand unabhängigen Leckstroms
US6967875B2 (en) * 2003-04-21 2005-11-22 United Microelectronics Corp. Static random access memory system with compensating-circuit for bitline leakage
CN106558329A (zh) * 2015-09-30 2017-04-05 展讯通信（上海）有限公司 一种单端存储器的差分读取电路及方法
CN106875963B (zh) * 2017-02-21 2019-05-14 中国科学院上海微系统与信息技术研究所 一种三维存储器读出电路及读出方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3277750D1 (de) * 1981-09-01 1988-01-07 Fujitsu Ltd Semi-conductor memory circuit
US4467451A (en) * 1981-12-07 1984-08-21 Hughes Aircraft Company Nonvolatile random access memory cell
US4494221A (en) * 1982-03-03 1985-01-15 Inmos Corporation Bit line precharging and equilibrating circuit
JPS61239493A (ja) * 1985-04-05 1986-10-24 Fujitsu Ltd 半導体記憶装置
JPS63131396A (ja) * 1986-11-20 1988-06-03 Ricoh Co Ltd 半導体メモリ装置のセンス回路
JPS63166090A (ja) * 1986-12-26 1988-07-09 Toshiba Corp スタティック型メモリ
JPH0760600B2 (ja) * 1987-08-19 1995-06-28 三菱電機株式会社 同期型記憶装置
JP2542022B2 (ja) * 1987-12-18 1996-10-09 沖電気工業株式会社 電界効果トランジスタ負荷回路
US4975879A (en) * 1989-07-17 1990-12-04 Advanced Micro Devices, Inc. Biasing scheme for FIFO memories

Also Published As

Publication number Publication date
DE4135686A1 (de) 1992-12-03
ITMI912808A1 (it) 1993-04-23
FR2677162A1 (fr) 1992-12-04
ITMI912808A0 (it) 1991-10-23
KR920022301A (ko) 1992-12-19
NL9101772A (nl) 1992-12-16
GB2256297A (en) 1992-12-02
GB9121767D0 (en) 1991-11-27
CN1067325A (zh) 1992-12-23

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Legal Events

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0001 Granted
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19961031