IT1251189B - Circuito decodificatore di righe per dispositivi di memoria non volatile. - Google Patents

Circuito decodificatore di righe per dispositivi di memoria non volatile.

Info

Publication number
IT1251189B
IT1251189B ITMI912319A ITMI912319A IT1251189B IT 1251189 B IT1251189 B IT 1251189B IT MI912319 A ITMI912319 A IT MI912319A IT MI912319 A ITMI912319 A IT MI912319A IT 1251189 B IT1251189 B IT 1251189B
Authority
IT
Italy
Prior art keywords
volatile memory
decoder circuit
memory devices
transistor
high voltage
Prior art date
Application number
ITMI912319A
Other languages
English (en)
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of ITMI912319A0 publication Critical patent/ITMI912319A0/it
Publication of ITMI912319A1 publication Critical patent/ITMI912319A1/it
Application granted granted Critical
Publication of IT1251189B publication Critical patent/IT1251189B/it

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory

Landscapes

  • Read Only Memory (AREA)
  • Non-Volatile Memory (AREA)

Abstract

E' descritto un circuito decodificatore di riga per un dispositivo di memoria non volatile, e il circuito è previsto per cancellare, programmare e leggere i dati dalla cella costituita da un transistor di selezione e da un transistor sensore. La richiesta alta tensione è applicata a linee di parole e linee di rilevazione da una singola porzione di generazione di alta tensione e, nel cancellare dati, una bassa tensione viene applicata alla linea delle parole. Un transistor per collegare una linea di rilevazione è collegata a ciascuna riga, in modo tale che il danno suscettibile di verificarsi allo strato di ossido di porta sarà ridotto, migliorando così la durata prevista della piastrina, e riducendo l'area della piastrina stessa.
ITMI912319A 1990-12-19 1991-08-29 Circuito decodificatore di righe per dispositivi di memoria non volatile. IT1251189B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900021060A KR940005695B1 (ko) 1990-12-19 1990-12-19 불휘발성 기억소자의 로우 디코더 회로

Publications (3)

Publication Number Publication Date
ITMI912319A0 ITMI912319A0 (it) 1991-08-29
ITMI912319A1 ITMI912319A1 (it) 1992-06-20
IT1251189B true IT1251189B (it) 1995-05-04

Family

ID=19307876

Family Applications (1)

Application Number Title Priority Date Filing Date
ITMI912319A IT1251189B (it) 1990-12-19 1991-08-29 Circuito decodificatore di righe per dispositivi di memoria non volatile.

Country Status (7)

Country Link
US (1) US5265062A (it)
JP (1) JPH0752593B2 (it)
KR (1) KR940005695B1 (it)
DE (1) DE4131261C2 (it)
FR (1) FR2670942B1 (it)
GB (1) GB2251104B (it)
IT (1) IT1251189B (it)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2822791B2 (ja) * 1992-06-30 1998-11-11 日本電気株式会社 半導体装置
FR2826496A1 (fr) * 2001-06-25 2002-12-27 St Microelectronics Sa Memoire eeprom protegee contre les effets d'un claquage de transistor d'acces
KR100481857B1 (ko) 2002-08-14 2005-04-11 삼성전자주식회사 레이아웃 면적을 줄이고 뱅크 마다 독립적인 동작을수행할 수 있는 디코더를 갖는 플레쉬 메모리 장치

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4266283A (en) * 1979-02-16 1981-05-05 Intel Corporation Electrically alterable read-mostly memory
EP0085260B1 (en) * 1981-12-29 1989-08-02 Fujitsu Limited Nonvolatile semiconductor memory circuit
JPS59124095A (ja) * 1982-12-29 1984-07-18 Fujitsu Ltd 半導体記憶装置
JPS6074577A (ja) * 1983-09-30 1985-04-26 Toshiba Corp 不揮発性半導体メモリ装置
JPH077599B2 (ja) * 1984-05-25 1995-01-30 株式会社日立製作所 半導体集積回路装置
DE3583669D1 (de) * 1984-12-25 1991-09-05 Toshiba Kawasaki Kk Nichtfluechtige halbleiterspeicheranordnung.
JPH0772996B2 (ja) * 1987-01-31 1995-08-02 株式会社東芝 不揮発性半導体メモリ
JPS6457438A (en) * 1987-08-28 1989-03-03 Mitsubishi Electric Corp Recording medium
JP2645417B2 (ja) * 1987-09-19 1997-08-25 富士通株式会社 不揮発性メモリ装置
FR2622038B1 (fr) * 1987-10-19 1990-01-19 Thomson Semiconducteurs Procede de programmation des cellules memoire d'une memoire et circuit pour la mise en oeuvre de ce procede
JPH021972A (ja) * 1988-06-10 1990-01-08 Mitsubishi Electric Corp 不揮発生半導体記憶装置
US5088060A (en) * 1989-03-08 1992-02-11 Kabushiki Kaisha Toshiba Electrically erasable programmable read-only memory with NAND memory cell structure
US5075890A (en) * 1989-05-02 1991-12-24 Kabushiki Kaisha Toshiba Electrically erasable programmable read-only memory with nand cell
JPH07114077B2 (ja) * 1989-06-01 1995-12-06 三菱電機株式会社 不揮発性半導体記憶装置

Also Published As

Publication number Publication date
FR2670942A1 (fr) 1992-06-26
ITMI912319A0 (it) 1991-08-29
JPH0752593B2 (ja) 1995-06-05
GB2251104A (en) 1992-06-24
GB2251104B (en) 1995-05-17
DE4131261A1 (de) 1992-07-02
FR2670942B1 (fr) 1994-03-11
ITMI912319A1 (it) 1992-06-20
US5265062A (en) 1993-11-23
KR920013467A (ko) 1992-07-29
JPH04259996A (ja) 1992-09-16
DE4131261C2 (de) 1996-01-11
GB9118665D0 (en) 1991-10-16
KR940005695B1 (ko) 1994-06-22

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Legal Events

Date Code Title Description
0001 Granted
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19970826