IT1241050B - Processo di formazione di una regione sepolta di drain o di collettore in dispositivi monolitici a semiconduttore. - Google Patents

Processo di formazione di una regione sepolta di drain o di collettore in dispositivi monolitici a semiconduttore.

Info

Publication number
IT1241050B
IT1241050B IT6609A IT660990A IT1241050B IT 1241050 B IT1241050 B IT 1241050B IT 6609 A IT6609 A IT 6609A IT 660990 A IT660990 A IT 660990A IT 1241050 B IT1241050 B IT 1241050B
Authority
IT
Italy
Prior art keywords
collector
drain
semiconductor devices
formation process
buried region
Prior art date
Application number
IT6609A
Other languages
English (en)
Other versions
IT9006609A0 (it
IT9006609A1 (it
Inventor
Raffaele Zambrano
Original Assignee
Cons Ric Microelettronica
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cons Ric Microelettronica filed Critical Cons Ric Microelettronica
Priority to IT6609A priority Critical patent/IT1241050B/it
Publication of IT9006609A0 publication Critical patent/IT9006609A0/it
Priority to DE69131390T priority patent/DE69131390T2/de
Priority to EP91200853A priority patent/EP0453026B1/en
Priority to JP3113788A priority patent/JPH065789A/ja
Publication of IT9006609A1 publication Critical patent/IT9006609A1/it
Priority to US07/967,553 priority patent/US5300451A/en
Application granted granted Critical
Publication of IT1241050B publication Critical patent/IT1241050B/it

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802Vertical DMOS transistors, i.e. VDMOS transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8222Bipolar technology
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8248Combination of bipolar and field-effect technology
    • H01L21/8249Bipolar and MOS technology
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843Source or drain regions of field-effect devices
    • H01L29/0847Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873Drain regions
    • H01L29/0878Impurity concentration or distribution
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712Vertical DMOS transistors, i.e. VDMOS transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843Source or drain regions of field-effect devices
    • H01L29/0847Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/126Power FETs
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/98Utilizing process equivalents or options

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)
  • Junction Field-Effect Transistors (AREA)
IT6609A 1990-04-20 1990-04-20 Processo di formazione di una regione sepolta di drain o di collettore in dispositivi monolitici a semiconduttore. IT1241050B (it)

Priority Applications (5)

Application Number Priority Date Filing Date Title
IT6609A IT1241050B (it) 1990-04-20 1990-04-20 Processo di formazione di una regione sepolta di drain o di collettore in dispositivi monolitici a semiconduttore.
DE69131390T DE69131390T2 (de) 1990-04-20 1991-04-11 Verfahren zur Herstellung einer vergrabenen Drain- oder Kollektorzone für monolythische Halbleiteranordnungen
EP91200853A EP0453026B1 (en) 1990-04-20 1991-04-11 Process for forming a buried drain or collector region in monolithic semiconductor devices
JP3113788A JPH065789A (ja) 1990-04-20 1991-04-19 埋込みドレイン又はコレクタ領域形成方法
US07/967,553 US5300451A (en) 1990-04-20 1992-10-27 Process for forming a buried drain or collector region in monolithic semiconductor devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT6609A IT1241050B (it) 1990-04-20 1990-04-20 Processo di formazione di una regione sepolta di drain o di collettore in dispositivi monolitici a semiconduttore.

Publications (3)

Publication Number Publication Date
IT9006609A0 IT9006609A0 (it) 1990-04-20
IT9006609A1 IT9006609A1 (it) 1991-10-20
IT1241050B true IT1241050B (it) 1993-12-29

Family

ID=11121360

Family Applications (1)

Application Number Title Priority Date Filing Date
IT6609A IT1241050B (it) 1990-04-20 1990-04-20 Processo di formazione di una regione sepolta di drain o di collettore in dispositivi monolitici a semiconduttore.

Country Status (5)

Country Link
US (1) US5300451A (it)
EP (1) EP0453026B1 (it)
JP (1) JPH065789A (it)
DE (1) DE69131390T2 (it)
IT (1) IT1241050B (it)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1244239B (it) * 1990-05-31 1994-07-08 Sgs Thomson Microelectronics Terminazione dello stadio di potenza di un dispositivo monolitico a semicondutture e relativo processo di fabbricazione
EP0683529B1 (en) * 1994-05-19 2003-04-02 Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno Power integrated circuit ("PIC") structure with a vertical IGBT, and manufacturing process thereof
US5702959A (en) * 1995-05-31 1997-12-30 Texas Instruments Incorporated Method for making an isolated vertical transistor
JPH10284753A (ja) * 1997-04-01 1998-10-23 Sony Corp 半導体装置及びその製造方法
TW515076B (en) * 2000-10-08 2002-12-21 Koninkl Philips Electronics Nv Protection diode for improved ruggedness of a radio frequency power transistor and self-defining method to manufacture such protection diode
JP4166010B2 (ja) * 2001-12-04 2008-10-15 富士電機デバイステクノロジー株式会社 横型高耐圧mosfet及びこれを備えた半導体装置
US7132715B2 (en) * 2004-05-21 2006-11-07 Fairchild Semiconductor Corporation Semiconductor device having a spacer layer doped with slower diffusing atoms than substrate
DE102004055183B3 (de) * 2004-11-16 2006-07-13 Atmel Germany Gmbh Integrierte Schaltung und Verfahren zur Herstellung einer integrierten Schaltung auf einem Halbleiterplättchen
CN100339946C (zh) * 2004-12-22 2007-09-26 中国电子科技集团公司第二十四研究所 小比导通电阻的集成化大电流功率器件结构的设计方法
JP5048242B2 (ja) * 2005-11-30 2012-10-17 オンセミコンダクター・トレーディング・リミテッド 半導体装置及びその製造方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5570064A (en) * 1978-11-21 1980-05-27 Toshiba Corp Multi-collector type transistor
JPS5750473A (en) * 1980-09-11 1982-03-24 Nec Corp Semiconductor integrated circuit device
DE3272436D1 (en) * 1982-05-06 1986-09-11 Itt Ind Gmbh Deutsche Method of making a monolithic integrated circuit with at least one isolated gate field effect transistor and one bipolar transistor
IT1214806B (it) * 1984-09-21 1990-01-18 Ates Componenti Elettron Dispositivo integrato monolitico di potenza e semiconduttore
IT1214808B (it) * 1984-12-20 1990-01-18 Ates Componenti Elettron Tico e semiconduttore processo per la formazione di uno strato sepolto e di una regione di collettore in un dispositivo monoli
JPS63198367A (ja) * 1987-02-13 1988-08-17 Toshiba Corp 半導体装置
JPH02105454A (ja) * 1988-10-14 1990-04-18 Olympus Optical Co Ltd 相補形mosfetの製造方法
US4914051A (en) * 1988-12-09 1990-04-03 Sprague Electric Company Method for making a vertical power DMOS transistor with small signal bipolar transistors
US5034337A (en) * 1989-02-10 1991-07-23 Texas Instruments Incorporated Method of making an integrated circuit that combines multi-epitaxial power transistors with logic/analog devices

Also Published As

Publication number Publication date
EP0453026A3 (it) 1995-02-15
IT9006609A0 (it) 1990-04-20
IT9006609A1 (it) 1991-10-20
EP0453026A2 (en) 1991-10-23
DE69131390T2 (de) 1999-11-18
DE69131390D1 (de) 1999-08-05
EP0453026B1 (en) 1999-06-30
US5300451A (en) 1994-04-05
JPH065789A (ja) 1994-01-14

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Legal Events

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0001 Granted
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19970429