IT1188283B - Circuito per aggiornare,controllare e correggere segnali di dati memorizzati in una memoria dinamica - Google Patents

Circuito per aggiornare,controllare e correggere segnali di dati memorizzati in una memoria dinamica

Info

Publication number
IT1188283B
IT1188283B IT19126/86A IT1912686A IT1188283B IT 1188283 B IT1188283 B IT 1188283B IT 19126/86 A IT19126/86 A IT 19126/86A IT 1912686 A IT1912686 A IT 1912686A IT 1188283 B IT1188283 B IT 1188283B
Authority
IT
Italy
Prior art keywords
dynamic memory
microprocessor
data
circuit
checking
Prior art date
Application number
IT19126/86A
Other languages
English (en)
Other versions
IT8619126A0 (it
Inventor
John Robert Ramsay
Zbigniew Boleslaw Styrna
Original Assignee
Mitel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitel Corp filed Critical Mitel Corp
Publication of IT8619126A0 publication Critical patent/IT8619126A0/it
Application granted granted Critical
Publication of IT1188283B publication Critical patent/IT1188283B/it

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
    • G06F11/106—Correcting systematically all correctable errors, i.e. scrubbing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G06F13/282—Cycle stealing DMA
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Databases & Information Systems (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
IT19126/86A 1985-08-15 1986-01-21 Circuito per aggiornare,controllare e correggere segnali di dati memorizzati in una memoria dinamica IT1188283B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CA000488829A CA1240066A (en) 1985-08-15 1985-08-15 Dynamic memory refresh and parity checking circuit

Publications (2)

Publication Number Publication Date
IT8619126A0 IT8619126A0 (it) 1986-01-21
IT1188283B true IT1188283B (it) 1988-01-07

Family

ID=4131191

Family Applications (1)

Application Number Title Priority Date Filing Date
IT19126/86A IT1188283B (it) 1985-08-15 1986-01-21 Circuito per aggiornare,controllare e correggere segnali di dati memorizzati in una memoria dinamica

Country Status (8)

Country Link
US (1) US4682328A (it)
JP (1) JPS6242396A (it)
CN (1) CN86100445A (it)
CA (1) CA1240066A (it)
DE (1) DE3620858A1 (it)
FR (1) FR2589600A1 (it)
GB (1) GB2179183B (it)
IT (1) IT1188283B (it)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4881205A (en) * 1987-04-21 1989-11-14 Casio Computer Co., Ltd. Compact electronic apparatus with a refresh unit for a dynamic type memory
JPH0831074B2 (ja) * 1987-11-25 1996-03-27 株式会社日立製作所 チャネル制御方式
AU628971B2 (en) * 1989-05-22 1992-09-24 Tandem Computers Incorporated Sequential parity correction
CA2021834C (en) * 1989-10-06 1993-12-21 Louis B. Capps, Jr. Personal computer memory bank parity error indicator
JP2960752B2 (ja) * 1990-06-07 1999-10-12 シャープ株式会社 半導体記憶装置
US5588112A (en) * 1992-12-30 1996-12-24 Digital Equipment Corporation DMA controller for memory scrubbing
US5778167A (en) * 1994-06-14 1998-07-07 Emc Corporation System and method for reassigning a storage location for reconstructed data on a persistent medium storage system
TW379298B (en) * 1996-09-30 2000-01-11 Toshiba Corp Memory updating history saving device and memory updating history saving method
US6301562B1 (en) 1999-04-27 2001-10-09 New Transducers Limited Speech recognition using both time encoding and HMM in parallel
US6993705B1 (en) * 2000-12-21 2006-01-31 Emc Corporation Cyclic redundancy check (CRC) parity check system and method
WO2002069152A1 (en) * 2001-02-24 2002-09-06 Blumrich Matthias A Managing coherence via put/get windows
US6760881B2 (en) 2001-10-16 2004-07-06 International Business Machines Corporation Method for combining refresh operation with parity validation in a DRAM-based content addressable memory (CAM)
DE10152235B4 (de) * 2001-10-20 2015-01-08 Robert Bosch Gmbh Verfahren zum Erkennen von Fehlern bei der Datenübertragung innerhalb eines CAN-Controllers und ein CAN-Controller zur Durchführung dieses Verfahrens
US7228469B2 (en) * 2003-01-02 2007-06-05 Fujitsu Limited Portable information device, method for recovering data in portable information device, and computer product
US7107390B2 (en) 2003-10-08 2006-09-12 Micron Technology, Inc. Parity-scanning and refresh in dynamic memory devices
CN100351802C (zh) * 2005-03-02 2007-11-28 华为技术有限公司 获取硬件信息的方法及系统
DE102005040917A1 (de) * 2005-08-30 2007-03-08 Robert Bosch Gmbh Datenverarbeitungssystem und Betriebsverfahren dafür
US9270976B2 (en) * 2005-11-02 2016-02-23 Exelis Inc. Multi-user stereoscopic 3-D panoramic vision system and method
TWI302311B (en) * 2006-06-09 2008-10-21 Innolux Display Corp Dynamic random access memory
US20160239441A1 (en) * 2015-02-13 2016-08-18 Qualcomm Incorporated Systems and methods for providing kernel scheduling of volatile memory maintenance events
WO2016157505A1 (ja) * 2015-04-02 2016-10-06 三菱電機株式会社 メモリチェック機能を有するｄｍａｃ
IT201700000509A1 (it) * 2017-01-03 2018-07-03 Gabriele Ferrandino Cronografo

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5324741A (en) * 1976-08-20 1978-03-07 Toshiba Corp Memory controller
US4183096A (en) * 1978-05-25 1980-01-08 Bell Telephone Laboratories, Incorporated Self checking dynamic memory system
JPS55105897A (en) * 1979-01-31 1980-08-13 Hitachi Koki Co Ltd Memory device
JPS5698780A (en) * 1979-12-29 1981-08-08 Nec Corp Semiconductor memory device
US4380812A (en) * 1980-04-25 1983-04-19 Data General Corporation Refresh and error detection and correction technique for a data processing system
GB2080586B (en) * 1980-07-25 1984-03-07 Honeywell Inf Systems Dynamic memory system with error correction
US4493081A (en) * 1981-06-26 1985-01-08 Computer Automation, Inc. Dynamic memory with error correction on refresh
US4556952A (en) * 1981-08-12 1985-12-03 International Business Machines Corporation Refresh circuit for dynamic memory of a data processor employing a direct memory access controller
US4542454A (en) * 1983-03-30 1985-09-17 Advanced Micro Devices, Inc. Apparatus for controlling access to a memory
DE3332601A1 (de) * 1983-09-09 1985-03-28 Siemens AG, 1000 Berlin und 8000 München Schaltungsanordnung zum registrieren von adressen von einen fehlerhaften speicherinhalt aufweisenden speicherzellen

Also Published As

Publication number Publication date
US4682328A (en) 1987-07-21
GB8602171D0 (en) 1986-03-05
JPS6242396A (ja) 1987-02-24
IT8619126A0 (it) 1986-01-21
CA1240066A (en) 1988-08-02
DE3620858C2 (it) 1990-11-08
GB2179183A (en) 1987-02-25
CN86100445A (zh) 1987-02-11
FR2589600A1 (fr) 1987-05-07
GB2179183B (en) 1990-01-04
DE3620858A1 (de) 1987-02-26

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