DE3587143D1 - Halbleiterspeichergeraet mit fehlererkennung/korrekturfunktion. - Google Patents

Halbleiterspeichergeraet mit fehlererkennung/korrekturfunktion.

Info

Publication number
DE3587143D1
DE3587143D1 DE8585115196T DE3587143T DE3587143D1 DE 3587143 D1 DE3587143 D1 DE 3587143D1 DE 8585115196 T DE8585115196 T DE 8585115196T DE 3587143 T DE3587143 T DE 3587143T DE 3587143 D1 DE3587143 D1 DE 3587143D1
Authority
DE
Germany
Prior art keywords
circuit
terminal
signal
high voltage
memory device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8585115196T
Other languages
English (en)
Other versions
DE3587143T2 (de
Inventor
Kaoru Nakagawa
Mitsugi Ogura
Kenji Natori
Fujio Masuoka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE3587143D1 publication Critical patent/DE3587143D1/de
Publication of DE3587143T2 publication Critical patent/DE3587143T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1076—Parity data used in redundant arrays of independent storages, e.g. in RAID systems
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
DE8585115196T 1984-12-04 1985-11-29 Halbleiterspeichergeraet mit fehlererkennung/korrekturfunktion. Expired - Lifetime DE3587143T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59256150A JPS61134988A (ja) 1984-12-04 1984-12-04 半導体メモリにおける誤り検出訂正機能制御系

Publications (2)

Publication Number Publication Date
DE3587143D1 true DE3587143D1 (de) 1993-04-08
DE3587143T2 DE3587143T2 (de) 1993-06-09

Family

ID=17288598

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8585115196T Expired - Lifetime DE3587143T2 (de) 1984-12-04 1985-11-29 Halbleiterspeichergeraet mit fehlererkennung/korrekturfunktion.

Country Status (4)

Country Link
US (1) US4706249A (de)
EP (1) EP0184737B1 (de)
JP (1) JPS61134988A (de)
DE (1) DE3587143T2 (de)

Families Citing this family (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62251949A (ja) * 1986-04-25 1987-11-02 Mitsubishi Electric Corp 記憶装置の誤り訂正方法
US4918385A (en) * 1987-05-18 1990-04-17 Hewlett-Packard Company Method and process for testing the reliability of integrated circuit (IC) chips and novel IC circuitry for accomplishing same
JPH01196647A (ja) * 1988-01-31 1989-08-08 Nec Corp 誤り訂正機能を有する記憶装置
US4989210A (en) * 1988-08-30 1991-01-29 Unisys Corporation Pipelined address check bit stack controller
US5228046A (en) * 1989-03-10 1993-07-13 International Business Machines Fault tolerant computer memory systems and components employing dual level error correction and detection with disablement feature
US5157670A (en) * 1989-12-04 1992-10-20 Avasem Corporation Error correction code interruption system
US5173905A (en) * 1990-03-29 1992-12-22 Micron Technology, Inc. Parity and error correction coding on integrated circuit addresses
KR950008789B1 (ko) * 1992-07-30 1995-08-08 삼성전자주식회사 멀티-이씨씨(ecc)회로를 내장하는 반도체 메모리 장치
US5367526A (en) * 1993-06-22 1994-11-22 Kong Edmund Y Memory module, parity bit emulator, and associated method for parity bit emulation
JP2669303B2 (ja) * 1993-08-03 1997-10-27 日本電気株式会社 ビットエラー訂正機能付き半導体メモリ
DE69526279T2 (de) * 1994-02-22 2002-10-02 Siemens Ag Flexible Fehlerkorrekturcode/Paritätsbit-Architektur
US5535226A (en) * 1994-05-31 1996-07-09 International Business Machines Corporation On-chip ECC status
JP3106947B2 (ja) * 1996-02-28 2000-11-06 日本電気株式会社 不揮発性半導体記憶装置
US6070262A (en) * 1997-04-04 2000-05-30 International Business Machines Corporation Reconfigurable I/O DRAM
DE19804035A1 (de) * 1998-02-02 1999-08-05 Siemens Ag Integrierter Speicher
JP4074029B2 (ja) * 1999-06-28 2008-04-09 株式会社東芝 フラッシュメモリ
US7032142B2 (en) * 2001-11-22 2006-04-18 Fujitsu Limited Memory circuit having parity cell array
US7099221B2 (en) 2004-05-06 2006-08-29 Micron Technology, Inc. Memory controller method and system compensating for memory cell data losses
US20060010339A1 (en) 2004-06-24 2006-01-12 Klein Dean A Memory system and method having selective ECC during low power refresh
US7340668B2 (en) 2004-06-25 2008-03-04 Micron Technology, Inc. Low power cost-effective ECC memory system and method
US7116602B2 (en) 2004-07-15 2006-10-03 Micron Technology, Inc. Method and system for controlling refresh to avoid memory cell data losses
US6965537B1 (en) 2004-08-31 2005-11-15 Micron Technology, Inc. Memory system and method using ECC to achieve low power refresh
JP4695385B2 (ja) 2004-11-30 2011-06-08 株式会社東芝 メモリカードおよびカードコントローラ
KR100694407B1 (ko) * 2005-04-21 2007-03-12 주식회사 하이닉스반도체 불량 셀 교정 회로를 포함하는 불휘발성 강유전체 메모리장치
US20070061669A1 (en) * 2005-08-30 2007-03-15 Major Karl L Method, device and system for detecting error correction defects
US7894289B2 (en) 2006-10-11 2011-02-22 Micron Technology, Inc. Memory system and method using partial ECC to achieve low power refresh and fast access to data
US7900120B2 (en) 2006-10-18 2011-03-01 Micron Technology, Inc. Memory system and method using ECC with flag bit to identify modified data
JP5042766B2 (ja) * 2007-10-03 2012-10-03 日立オートモティブシステムズ株式会社 制御装置、および制御装置のメモリ初期化方法
JP2009093714A (ja) 2007-10-04 2009-04-30 Panasonic Corp 半導体記憶装置
JP4856110B2 (ja) * 2008-03-01 2012-01-18 株式会社東芝 チェンサーチ装置およびチェンサーチ方法
US8392779B2 (en) * 2008-04-25 2013-03-05 Qimonda Ag Interface voltage adjustment based on error detection
KR101668934B1 (ko) * 2012-03-12 2016-10-28 인텔 코포레이션 분배된 코드워드 부분들
US10908996B2 (en) 2019-02-22 2021-02-02 Intel Corporation Distribution of a codeword across individual storage units to reduce the bit error rate

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3836957A (en) * 1973-06-26 1974-09-17 Ibm Data storage system with deferred error detection
US4058851A (en) * 1976-10-18 1977-11-15 Sperry Rand Corporation Conditional bypass of error correction for dual memory access time selection
JPS592057B2 (ja) * 1979-02-07 1984-01-17 株式会社日立製作所 エラ−訂正・検出方式
JPS5622278A (en) * 1979-07-27 1981-03-02 Fujitsu Ltd Decoder selection system
JPS5622294A (en) * 1979-07-31 1981-03-02 Nippon Telegr & Teleph Corp <Ntt> Memory circuit
JPS5650357A (en) * 1979-09-29 1981-05-07 Canon Inc Developing method
US4336611A (en) * 1979-12-03 1982-06-22 Honeywell Information Systems Inc. Error correction apparatus and method
US4412314A (en) * 1980-06-02 1983-10-25 Mostek Corporation Semiconductor memory for use in conjunction with error detection and correction circuit
JPS573164A (en) * 1980-06-04 1982-01-08 Nippon Denso Co Ltd Microcomputer control device
JPS5774893A (en) * 1980-10-27 1982-05-11 Nec Corp Storage device
US4493081A (en) * 1981-06-26 1985-01-08 Computer Automation, Inc. Dynamic memory with error correction on refresh
JPS5968900A (ja) * 1982-10-13 1984-04-18 Nippon Telegr & Teleph Corp <Ntt> メモリ集積回路
JPS6011952A (ja) * 1983-07-01 1985-01-22 Mitsubishi Electric Corp 誤り訂正機構付半導体メモリ装置
JPS60173644A (ja) * 1984-02-13 1985-09-07 Fujitsu Ltd 半導体記憶装置

Also Published As

Publication number Publication date
EP0184737B1 (de) 1993-03-03
DE3587143T2 (de) 1993-06-09
EP0184737A2 (de) 1986-06-18
EP0184737A3 (en) 1988-09-14
JPS61134988A (ja) 1986-06-23
US4706249A (en) 1987-11-10

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)