GB2080586B - Dynamic memory system with error correction - Google Patents

Dynamic memory system with error correction

Info

Publication number
GB2080586B
GB2080586B GB8122683A GB8122683A GB2080586B GB 2080586 B GB2080586 B GB 2080586B GB 8122683 A GB8122683 A GB 8122683A GB 8122683 A GB8122683 A GB 8122683A GB 2080586 B GB2080586 B GB 2080586B
Authority
GB
United Kingdom
Prior art keywords
error correction
memory system
dynamic memory
dynamic
correction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB8122683A
Other versions
GB2080586A (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull HN Information Systems Italia SpA
Bull HN Information Systems Inc
Original Assignee
Honeywell Information Systems Italia SpA
Honeywell Information Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US06/172,486 external-priority patent/US4359771A/en
Priority claimed from US06/172,485 external-priority patent/US4369510A/en
Application filed by Honeywell Information Systems Italia SpA, Honeywell Information Systems Inc filed Critical Honeywell Information Systems Italia SpA
Publication of GB2080586A publication Critical patent/GB2080586A/en
Application granted granted Critical
Publication of GB2080586B publication Critical patent/GB2080586B/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
    • G06F11/106—Correcting systematically all correctable errors, i.e. scrubbing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
GB8122683A 1980-07-25 1981-07-23 Dynamic memory system with error correction Expired GB2080586B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/172,486 US4359771A (en) 1980-07-25 1980-07-25 Method and apparatus for testing and verifying the operation of error control apparatus within a memory
US06/172,485 US4369510A (en) 1980-07-25 1980-07-25 Soft error rewrite control system

Publications (2)

Publication Number Publication Date
GB2080586A GB2080586A (en) 1982-02-03
GB2080586B true GB2080586B (en) 1984-03-07

Family

ID=26868137

Family Applications (1)

Application Number Title Priority Date Filing Date
GB8122683A Expired GB2080586B (en) 1980-07-25 1981-07-23 Dynamic memory system with error correction

Country Status (1)

Country Link
GB (1) GB2080586B (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0082533A3 (en) * 1981-12-21 1985-11-27 Siemens Aktiengesellschaft Method of acquisition and correction of data errors, and device to perform the method
CA1240066A (en) * 1985-08-15 1988-08-02 John R. Ramsay Dynamic memory refresh and parity checking circuit

Also Published As

Publication number Publication date
GB2080586A (en) 1982-02-03

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Legal Events

Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee

Effective date: 19950723