HK178495A - Method and circuit arrangement for assuring the bit synchronization of a data block in a receiver - Google Patents

Method and circuit arrangement for assuring the bit synchronization of a data block in a receiver

Info

Publication number
HK178495A
HK178495A HK178495A HK178495A HK178495A HK 178495 A HK178495 A HK 178495A HK 178495 A HK178495 A HK 178495A HK 178495 A HK178495 A HK 178495A HK 178495 A HK178495 A HK 178495A
Authority
HK
Hong Kong
Prior art keywords
bit
clock
phase
receiver
data block
Prior art date
Application number
HK178495A
Other languages
English (en)
Inventor
Manfred Tasto Ph D
Georg Ing Grad Ranner
Rainer Dipl-Ing Blaesius (Fh)
Christian Dipl-Ing Behr (Fh)
Original Assignee
Philips Electronics Nv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Electronics Nv filed Critical Philips Electronics Nv
Publication of HK178495A publication Critical patent/HK178495A/xx

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
    • H04L7/0338—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals the correction of the phase error being performed by a feed forward loop
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
    • H04L7/046—Speed or phase control by synchronisation signals using special codes as synchronising signal using a dotting sequence

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Mobile Radio Communication Systems (AREA)
  • Communication Control (AREA)
HK178495A 1986-08-09 1995-11-23 Method and circuit arrangement for assuring the bit synchronization of a data block in a receiver HK178495A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE3627135A DE3627135C2 (de) 1986-08-09 1986-08-09 Bitsynchronisation eines Datenblocks in einem Empfänger

Publications (1)

Publication Number Publication Date
HK178495A true HK178495A (en) 1995-12-01

Family

ID=6307122

Family Applications (1)

Application Number Title Priority Date Filing Date
HK178495A HK178495A (en) 1986-08-09 1995-11-23 Method and circuit arrangement for assuring the bit synchronization of a data block in a receiver

Country Status (10)

Country Link
US (1) US4817117A (xx)
EP (1) EP0256595B1 (xx)
JP (1) JPH07112187B2 (xx)
KR (1) KR880003494A (xx)
AT (1) ATE98412T1 (xx)
DE (2) DE3627135C2 (xx)
DK (1) DK409787A (xx)
ES (1) ES2048731T3 (xx)
FI (1) FI92359C (xx)
HK (1) HK178495A (xx)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4803703A (en) * 1987-04-30 1989-02-07 Motorola, Inc. Apparatus and method for fine synchronization of a communication receiver
DE3832946A1 (de) * 1988-09-28 1990-04-05 Siemens Ag Verfahren zur verschluesselung digitaler zeitmultiplexsignale
JPH0771057B2 (ja) * 1990-02-28 1995-07-31 松下電器産業株式会社 ディジタル移動無線用フレーム同期方法
JPH0778774B2 (ja) * 1991-02-22 1995-08-23 インターナショナル・ビジネス・マシーンズ・コーポレイション 短待ち時間データ回復装置及びメッセージデータの同期化方法
DE4132200A1 (de) * 1991-09-27 1993-04-01 Aeg Mobile Communication Zeitmultiplex-verfahren zur bestimmung der mittleren phasenaenderung eines empfangssignals
DE4224527A1 (de) * 1992-07-24 1994-01-27 Siemens Ag Verfahren zur Durchschaltung von Digitalsignalen
US5323421A (en) * 1992-09-30 1994-06-21 Motorola, Inc. Method and apparatus of estimating channel quality in a receiver
DE4333000C2 (de) * 1993-09-28 1997-10-16 Siemens Ag Verfahren und Anordnung zum Synchronisieren von Basisstationen in einem mehrzellularen, drahtlosen Fernsprechsystem
DE4333397C1 (de) * 1993-09-30 1994-12-08 Siemens Ag Verfahren und Anordnung zur Übertragung eines Digitalsignals
US5787078A (en) * 1994-03-09 1998-07-28 Alcatel N.V. Frame Synchronization method
GB2315194B (en) * 1996-07-11 2000-11-15 Nokia Mobile Phones Ltd Method and apparatus for resynchronizing two system clocks
DE19639309B4 (de) * 1996-09-25 2013-12-05 Rohde & Schwarz Gmbh & Co. Kg Verfahren zum Bestimmen der zeitlichen Lage einer Synchronisationsfolge in einem empfangenen Datenstrom mittels Rahmensynchronisation
DE19640315C1 (de) * 1996-09-30 1998-02-26 Siemens Ag Verfahren und Vorrichtung zur Aktionssteuerung in einem Zeitschlitzverfahren
US7065050B1 (en) * 1998-07-08 2006-06-20 Broadcom Corporation Apparatus and method for controlling data flow in a network switch
DE10004874C2 (de) 2000-02-04 2002-01-17 Infineon Technologies Ag Einrichtung zur Durchführung von Suchprozeduren in einem Mobilfunkempfänger
US8775707B2 (en) 2010-12-02 2014-07-08 Blackberry Limited Single wire bus system
US9479275B2 (en) 2012-06-01 2016-10-25 Blackberry Limited Multiformat digital audio interface
CN104541473B (zh) 2012-06-01 2017-09-12 黑莓有限公司 基于概率方法的用于保证多格式音频系统中的锁定的通用同步引擎
US9461812B2 (en) * 2013-03-04 2016-10-04 Blackberry Limited Increased bandwidth encoding scheme
US9473876B2 (en) 2014-03-31 2016-10-18 Blackberry Limited Method and system for tunneling messages between two or more devices using different communication protocols

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1805463B2 (de) * 1968-10-26 1971-10-14 Blocksynchronisationsverfahren fuer zeitmultiplexsysteme mit pulscodemodulation
DE2219016C3 (de) * 1972-04-19 1978-11-30 Standard Elektrik Lorenz Ag, 7000 Stuttgart Verfahren zur empfangsseitigen Phasensynchronisation auf die Phasenlage des Bittaktes eines empfangenen Datenblocks
FR2283592A1 (fr) * 1974-08-27 1976-03-26 Thomson Csf Dispositif extracteur de synchronisation et systeme de transmission d'informations comportant un tel dispositif
US4189622A (en) * 1975-10-17 1980-02-19 Ncr Corporation Data communication system and bit-timing circuit
DE3012075A1 (de) * 1979-11-20 1981-10-08 Standard Elektrik Lorenz Ag, 7000 Stuttgart Schaltungsanordnung zur bitsynchronisation
US4312074A (en) * 1980-02-07 1982-01-19 Motorola, Inc. Method and apparatus for detecting a data signal including repeated data words
US4541104A (en) * 1982-06-10 1985-09-10 Nec Corporation Framing circuit for digital system
FR2549323B1 (fr) * 1983-07-12 1985-10-25 Lignes Telegraph Telephon Dispositif de synchronisation pour transmission numerique avec trames, et recepteur comportant un tel dispositif
US4672639A (en) * 1984-05-24 1987-06-09 Kabushiki Kaisha Toshiba Sampling clock pulse generator
US4663765A (en) * 1985-02-01 1987-05-05 General Electric Company Data muting method and apparatus for audo-digital communications systems

Also Published As

Publication number Publication date
EP0256595A3 (en) 1990-03-21
US4817117A (en) 1989-03-28
EP0256595B1 (de) 1993-12-08
FI92359B (fi) 1994-07-15
ATE98412T1 (de) 1993-12-15
ES2048731T3 (es) 1994-04-01
JPS63100838A (ja) 1988-05-02
FI873405A (fi) 1988-02-10
JPH07112187B2 (ja) 1995-11-29
DE3788383D1 (de) 1994-01-20
KR880003494A (ko) 1988-05-17
FI92359C (fi) 1994-10-25
DE3627135A1 (de) 1988-02-11
EP0256595A2 (de) 1988-02-24
DK409787A (da) 1988-02-10
FI873405A0 (fi) 1987-08-05
DE3627135C2 (de) 1994-11-24
DK409787D0 (da) 1987-08-06

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Legal Events

Date Code Title Description
PC Patent ceased (i.e. patent has lapsed due to the failure to pay the renewal fee)