EP0256595A3 - Method and circuit arrangement for assuring the bit synchronization of a data block in a receiver - Google Patents

Method and circuit arrangement for assuring the bit synchronization of a data block in a receiver Download PDF

Info

Publication number
EP0256595A3
EP0256595A3 EP87201487A EP87201487A EP0256595A3 EP 0256595 A3 EP0256595 A3 EP 0256595A3 EP 87201487 A EP87201487 A EP 87201487A EP 87201487 A EP87201487 A EP 87201487A EP 0256595 A3 EP0256595 A3 EP 0256595A3
Authority
EP
European Patent Office
Prior art keywords
bit
clock
phase
receiver
data block
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP87201487A
Other languages
German (de)
Other versions
EP0256595A2 (en
EP0256595B1 (en
Inventor
Manfred Tasto, Ph. D.
Georg Ing. Grad. Ranner
Rainer Dipl.-Ing. Blasius (Fh)
Christian Dipl.-Ing. Behr (Fh)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Philips Patentverwaltung GmbH
Philips Gloeilampenfabrieken NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Patentverwaltung GmbH, Philips Gloeilampenfabrieken NV filed Critical Philips Patentverwaltung GmbH
Priority to AT87201487T priority Critical patent/ATE98412T1/en
Publication of EP0256595A2 publication Critical patent/EP0256595A2/en
Publication of EP0256595A3 publication Critical patent/EP0256595A3/en
Application granted granted Critical
Publication of EP0256595B1 publication Critical patent/EP0256595B1/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
    • H04L7/0338—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals the correction of the phase error being performed by a feed forward loop
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
    • H04L7/046—Speed or phase control by synchronisation signals using special codes as synchronising signal using a dotting sequence

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Mobile Radio Communication Systems (AREA)
  • Communication Control (AREA)

Abstract

For synchronizing a data block in a receiver, there are transmitted consecutively and prior to the data block: a first bit sequence of alternating "0" and "1" levels for determining the bit clock and a second bit sequence for determining the block synchronization by correlation. In known methods of determining the bit clock, the phase range of the individual bits of the received digital signal is divided into sub-intervals and the phase position of the bit clock is determined on account of the number of edges in these sub-intervals. In order to avoid fading and phase jitter having a detrimental effect on the bit synchronism, more specifically when transmitting through radio transmission links, N-phase-shifted clocks having the same clock frequency are generated in the receiver by means of which the first bit sequence is sampled. The clock for which the number of sample-value changes of the first bit sequence is established as having a predeterminable minimum value during a predeterminable time-interval is utilized as the phase synchronous bit clock.
EP87201487A 1986-08-09 1987-08-05 Method and circuit arrangement for assuring the bit synchronization of a data block in a receiver Expired - Lifetime EP0256595B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AT87201487T ATE98412T1 (en) 1986-08-09 1987-08-05 METHOD AND CIRCUIT ARRANGEMENT TO ENSURE BIT SYNCHRONIZATION OF A DATA BLOCK IN A RECEIVER.

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE3627135A DE3627135C2 (en) 1986-08-09 1986-08-09 Bit synchronization of a data block in a receiver
DE3627135 1986-08-09

Publications (3)

Publication Number Publication Date
EP0256595A2 EP0256595A2 (en) 1988-02-24
EP0256595A3 true EP0256595A3 (en) 1990-03-21
EP0256595B1 EP0256595B1 (en) 1993-12-08

Family

ID=6307122

Family Applications (1)

Application Number Title Priority Date Filing Date
EP87201487A Expired - Lifetime EP0256595B1 (en) 1986-08-09 1987-08-05 Method and circuit arrangement for assuring the bit synchronization of a data block in a receiver

Country Status (10)

Country Link
US (1) US4817117A (en)
EP (1) EP0256595B1 (en)
JP (1) JPH07112187B2 (en)
KR (1) KR880003494A (en)
AT (1) ATE98412T1 (en)
DE (2) DE3627135C2 (en)
DK (1) DK409787A (en)
ES (1) ES2048731T3 (en)
FI (1) FI92359C (en)
HK (1) HK178495A (en)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4803703A (en) * 1987-04-30 1989-02-07 Motorola, Inc. Apparatus and method for fine synchronization of a communication receiver
DE3832946A1 (en) * 1988-09-28 1990-04-05 Siemens Ag Method for encoding digital time-division multiplex signals
JPH0771057B2 (en) * 1990-02-28 1995-07-31 松下電器産業株式会社 Frame synchronization method for digital mobile radio
JPH0778774B2 (en) * 1991-02-22 1995-08-23 インターナショナル・ビジネス・マシーンズ・コーポレイション Short latency data recovery device and message data synchronization method
DE4132200A1 (en) * 1991-09-27 1993-04-01 Aeg Mobile Communication TIME MULTIPLEXING METHOD FOR DETERMINING THE MEDIUM PHASE CHANGE OF A RECEIVE SIGNAL
DE4224527A1 (en) * 1992-07-24 1994-01-27 Siemens Ag Through switching of digital signals - transmitting signals in frame with eighteen bit frame identification word with more signal edges than required for synchronisation
US5323421A (en) * 1992-09-30 1994-06-21 Motorola, Inc. Method and apparatus of estimating channel quality in a receiver
DE4333000C2 (en) * 1993-09-28 1997-10-16 Siemens Ag Method and arrangement for synchronizing base stations in a multi-cellular, wireless telephone system
DE4333397C1 (en) * 1993-09-30 1994-12-08 Siemens Ag Method and arrangement for the transmission of a digital signal
US5787078A (en) * 1994-03-09 1998-07-28 Alcatel N.V. Frame Synchronization method
GB2315194B (en) * 1996-07-11 2000-11-15 Nokia Mobile Phones Ltd Method and apparatus for resynchronizing two system clocks
DE19639309B4 (en) * 1996-09-25 2013-12-05 Rohde & Schwarz Gmbh & Co. Kg Method for determining the time position of a synchronization sequence in a received data stream by means of frame synchronization
DE19640315C1 (en) * 1996-09-30 1998-02-26 Siemens Ag Method and device for action control in a time slot method
US6735679B1 (en) * 1998-07-08 2004-05-11 Broadcom Corporation Apparatus and method for optimizing access to memory
DE10004874C2 (en) * 2000-02-04 2002-01-17 Infineon Technologies Ag Device for performing search procedures in a mobile radio receiver
US8775707B2 (en) 2010-12-02 2014-07-08 Blackberry Limited Single wire bus system
EP2856690B1 (en) 2012-06-01 2020-12-02 BlackBerry Limited Universal synchronization engine based on probabilistic methods for guarantee of lock in multiformat audio systems
US9479275B2 (en) 2012-06-01 2016-10-25 Blackberry Limited Multiformat digital audio interface
US9461812B2 (en) * 2013-03-04 2016-10-04 Blackberry Limited Increased bandwidth encoding scheme
US9473876B2 (en) 2014-03-31 2016-10-18 Blackberry Limited Method and system for tunneling messages between two or more devices using different communication protocols

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2283592A1 (en) * 1974-08-27 1976-03-26 Thomson Csf SYNCHRONIZATION EXTRACTOR AND INFORMATION TRANSMISSION SYSTEM INCLUDING SUCH A DEVICE
US4189622A (en) * 1975-10-17 1980-02-19 Ncr Corporation Data communication system and bit-timing circuit
DE3012075A1 (en) * 1979-11-20 1981-10-08 Standard Elektrik Lorenz Ag, 7000 Stuttgart Receiving circuit for data bits with jitter - has multiple pre-sampling circuit to select mid-bit clock pulse timing
EP0165498A1 (en) * 1984-05-24 1985-12-27 Kabushiki Kaisha Toshiba Sampling clock pulse generator

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1805463B2 (en) * 1968-10-26 1971-10-14 BLOCK SYNCHRONIZATION METHOD FOR TIME MULTIPLEX SYSTEMS WITH PULSE CODE MODULATION
DE2219016C3 (en) * 1972-04-19 1978-11-30 Standard Elektrik Lorenz Ag, 7000 Stuttgart Method for phase synchronization at the receiving end to the phase position of the bit clock of a received data block
US4312074A (en) * 1980-02-07 1982-01-19 Motorola, Inc. Method and apparatus for detecting a data signal including repeated data words
US4541104A (en) * 1982-06-10 1985-09-10 Nec Corporation Framing circuit for digital system
FR2549323B1 (en) * 1983-07-12 1985-10-25 Lignes Telegraph Telephon SYNCHRONIZATION DEVICE FOR DIGITAL TRANSMISSION WITH FRAMES, AND RECEIVER COMPRISING SUCH A DEVICE
US4663765A (en) * 1985-02-01 1987-05-05 General Electric Company Data muting method and apparatus for audo-digital communications systems

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2283592A1 (en) * 1974-08-27 1976-03-26 Thomson Csf SYNCHRONIZATION EXTRACTOR AND INFORMATION TRANSMISSION SYSTEM INCLUDING SUCH A DEVICE
US4189622A (en) * 1975-10-17 1980-02-19 Ncr Corporation Data communication system and bit-timing circuit
DE3012075A1 (en) * 1979-11-20 1981-10-08 Standard Elektrik Lorenz Ag, 7000 Stuttgart Receiving circuit for data bits with jitter - has multiple pre-sampling circuit to select mid-bit clock pulse timing
EP0165498A1 (en) * 1984-05-24 1985-12-27 Kabushiki Kaisha Toshiba Sampling clock pulse generator

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
NACHRICHTENTECHNIK, Band 22, Nr. 6, Juni 1972, Seiten 197-199; W. GLASER: "Zur Erkennung einer gerasterten in einer stochastischen Binärimpulsfolge" *

Also Published As

Publication number Publication date
EP0256595A2 (en) 1988-02-24
FI92359C (en) 1994-10-25
FI873405A (en) 1988-02-10
JPH07112187B2 (en) 1995-11-29
DK409787D0 (en) 1987-08-06
DE3627135C2 (en) 1994-11-24
KR880003494A (en) 1988-05-17
DE3627135A1 (en) 1988-02-11
FI92359B (en) 1994-07-15
DK409787A (en) 1988-02-10
US4817117A (en) 1989-03-28
ATE98412T1 (en) 1993-12-15
JPS63100838A (en) 1988-05-02
EP0256595B1 (en) 1993-12-08
FI873405A0 (en) 1987-08-05
ES2048731T3 (en) 1994-04-01
HK178495A (en) 1995-12-01
DE3788383D1 (en) 1994-01-20

Similar Documents

Publication Publication Date Title
EP0256595A3 (en) Method and circuit arrangement for assuring the bit synchronization of a data block in a receiver
US6483856B1 (en) GPS synchronized data communications link
CA2349344A1 (en) Reducing waiting time jitter
GB0022608D0 (en) Method of synchronising data
AU7464081A (en) Data synchronisation
SE9202598D0 (en) TIME SYNCHRONIZATION OF A RECEIVER IN A DIGITAL RADIO TELEPHONE SYSTEM
JPS5639694A (en) Method and device for synchrnonizing timing in transmission of digital information signal
CZ285354B6 (en) Process for synchronization of clock sample signal with received data signal, and apparatus for making the same
ES489851A1 (en) Method of synchronizing a quadphase receiver and clock synchronization device for carrying out the method
EP0666677A2 (en) Transmissions synchronization in a digital cordless telecommunication system
JP2693758B2 (en) Frame pulse generation method
ATE14058T1 (en) DIGITAL MESSAGE TRANSMISSION SYSTEM.
EP0720319A2 (en) Clock recovery extrapolation
JP2003134098A (en) Serial receiver
EP0602898B1 (en) Method and apparatus for synchronizing transmission of modem
JPS6058616B2 (en) Communication device
KR950001507B1 (en) Virtual container 12 signal mapper
JPS57173242A (en) Synchronizing circuit
JPS6316194Y2 (en)
CA2173773A1 (en) Method and apparatus for regenerating the symbol clock of a cellular telephone following a sleep cycle
JPS5950645A (en) Independent synchronizing system
JPS6072336A (en) Clock synchronizing system
JPH0542210B2 (en)
SU1840576A1 (en) System for synchronizing timers via radio channel
JPS5799050A (en) Baud rate remote setting system

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Kind code of ref document: A2

Designated state(s): AT BE CH DE ES FR GB IT LI SE

PUAL Search report despatched

Free format text: ORIGINAL CODE: 0009013

AK Designated contracting states

Kind code of ref document: A3

Designated state(s): AT BE CH DE ES FR GB IT LI SE

17P Request for examination filed

Effective date: 19900919

17Q First examination report despatched

Effective date: 19920416

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): AT BE CH DE ES FR GB IT LI SE

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: BE

Effective date: 19931208

REF Corresponds to:

Ref document number: 98412

Country of ref document: AT

Date of ref document: 19931215

Kind code of ref document: T

REF Corresponds to:

Ref document number: 3788383

Country of ref document: DE

Date of ref document: 19940120

ITF It: translation for a ep patent filed

Owner name: ING. C. GREGORJ S.P.A.

GBT Gb: translation of ep patent filed (gb section 77(6)(a)/1977)

Effective date: 19940225

ET Fr: translation filed
REG Reference to a national code

Ref country code: ES

Ref legal event code: FG2A

Ref document number: 2048731

Country of ref document: ES

Kind code of ref document: T3

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: ES

Payment date: 19940803

Year of fee payment: 8

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: AT

Effective date: 19940805

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: SE

Payment date: 19940826

Year of fee payment: 8

PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: CH

Payment date: 19941122

Year of fee payment: 8

26N No opposition filed
EAL Se: european patent in force in sweden

Ref document number: 87201487.3

ITPR It: changes in ownership of a european patent

Owner name: CAMBIO RAGIONE SOCIALE;PHILIPS ELECTRONICS N.V.

REG Reference to a national code

Ref country code: CH

Ref legal event code: PFA

Free format text: PHILIPS ELECTRONICS N.V.

REG Reference to a national code

Ref country code: FR

Ref legal event code: CD

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: SE

Effective date: 19950806

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: ES

Free format text: LAPSE BECAUSE OF THE APPLICANT RENOUNCES

Effective date: 19950807

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: LI

Effective date: 19950831

Ref country code: CH

Effective date: 19950831

REG Reference to a national code

Ref country code: CH

Ref legal event code: PL

EUG Se: european patent has lapsed

Ref document number: 87201487.3

REG Reference to a national code

Ref country code: FR

Ref legal event code: CD

REG Reference to a national code

Ref country code: ES

Ref legal event code: FD2A

Effective date: 19991007

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: FR

Payment date: 20010824

Year of fee payment: 15

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: GB

Payment date: 20010831

Year of fee payment: 15

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 20011015

Year of fee payment: 15

REG Reference to a national code

Ref country code: GB

Ref legal event code: IF02

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GB

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20020805

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20030301

GBPC Gb: european patent ceased through non-payment of renewal fee

Effective date: 20020805

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: FR

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20030430

REG Reference to a national code

Ref country code: FR

Ref legal event code: ST

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IT

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES;WARNING: LAPSES OF ITALIAN PATENTS WITH EFFECTIVE DATE BEFORE 2007 MAY HAVE OCCURRED AT ANY TIME BEFORE 2007. THE CORRECT EFFECTIVE DATE MAY BE DIFFERENT FROM THE ONE RECORDED.

Effective date: 20050805