JPS6058616B2 - Communication device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a communication device that disassembles and assembles an envelope in an envelope method used as a method of synchronous data communication. The present invention provides envelope synchronous communication that is automatically followed by such a communication device.

A conventional envelope type communication device is shown in FIG. In FIG. 1, 1 is an input transmission line through which the envelope is sent, 2 is a digital phase synchronization circuit, 3 is a digital phase synchronization circuit clock, 4 is a bit clock synchronized with the data of input transmission line 1, 5 is a receiving section, 6 is an envelope synchronization circuit, 7 is a transmitter, 8 is an output transmission line for sending out the envelope, 30 is an output indicating that the envelope is out of synchronization, 38 is a reception data output, 39 is a reception control information output, 40 is a transmission data input, 41 is the transmission control information input. Data and control information are sent to the input transmission line 1 in an envelope. The configuration of the envelope is shown in Figure 2. In Figure 2, 10 is a continuous envelope with F bits, 1,
It is a repeating 0 and is used for envelope synchronization. Reference numeral 11 is a data bit in which 3 bits of data are inserted.

12 carries control information in s bits.

These 8-bit envelopes are continuously transmitted and received on the transmission line. This concludes the explanation of the envelope. In FIG. 1, a digital phase synchronization circuit 2 extracts a bit clock 4 synchronized with data from a data change point of an input transmission line 1. The envelope synchronization circuit 6 samples the data on the input transmission line 1 at the bit clock 4, detects repetition of 1 and 0 of the F bit, and performs envelope synchronization. The receiving section 5 uses the bit clock 4 and the envelope synchronization information from the envelope J synchronization circuit 6 to
The envelope from is decomposed into bit strings of data and control information and outputs a received data output 38 and a received control information output 39, respectively. The transmitter 7 assembles the data and control information input from the transmit data input 40 and the transmit control information input 471 into an envelope, and transmits it to the output transmission line 8 in synchronization with the bit clock 4. The above is the explanation of the envelope type communication device. In such a conventional envelope type communication device, the internal transmission/reception clock 4 operates in synchronization with the clock of the other party, but since the speed of the digital phase synchronization circuit clock 3 is fixed, the speed of data that can be synchronized is limited. The disadvantage is that the range is narrow, and when communicating, the communication speed must be matched with that of the other party in advance.

In this invention, when the communication speed with the other party is limited to several types, no matter which speed the other party communicates at, the communication device automatically detects the speed and adjusts the clock of the digital phase synchronized circuit. The feature is that communication is performed in synchronization with the communication speed of the other party by switching the speed, and that there is no need for additional agreements by using an envelope to detect the communication speed.The purpose is to communicate with the other party. The purpose is to eliminate special measures to match the communication speed of

Embodiments of the present invention will be described below with reference to the drawings.

Here, the communication speed detection means of the present invention will be explained. FIG. 3 shows the envelope waveform of the input transmission line 1 at the time of envelope synchronization pull-in, where 13 is the value of each bit of the envelope, and 42 is a mark indicating the change point of the waveform of the input transmission line 1.

In the envelope method, data bits 11 are all set to 1 and control information 12 is set to O at the time of envelope synchronization pull-in before communication. Therefore, a waveform pattern as shown in FIG. 3 is obtained, and speed can be detected using this pattern. FIG. 4 shows an embodiment of the communication speed synchronization circuit according to the present invention. In this invention, by using the output 3 of this circuit as the digital phase synchronization circuit clock 3 of FIG. 1, the communication speed of the other party is automatically adjusted. Enables synchronous communication.

This communication speed synchronization circuit detects the speed by utilizing the fact that in the waveform of the input transmission line 1, the mark 42 indicating a waveform change occurs twice during one envelope. In FIG. 4, 15 is a change point detection circuit, 16 is its output, 17 is a reversible counter, 18 is its carry output, 19 is its carry down output, 21 and 23 are the outputs of AND gates 20 and 22, 25 is the output of the pointer 24; 26 is a clock selection circuit that selects a clock based on the output 25 of the pointer 24;
Its output 3 becomes a digital phase synchronized circuit clock 3.

Reference numeral 27 denotes a group of clocks selected by the selection circuit 26, which are connected so that the smaller the value of the pointer 24, the faster the clock is selected.

28 is a frequency divider whose frequency division ratio is selected to be four times that of the digital phase synchronized circuit 2, and 29 is a frequency divided output.

Here, the operations of the reversible counter 17 and pointer 24 will be described. In the following explanation, the reversible counter 17 is assumed to be 3 bits, and the values of the 3 bits are expressed in a table as numbers from 0 to 7.

The operation of the reversible counter 17 is such that the value increases by one due to the pulse of the frequency division output 29, the value decreases by one due to the pulse of the output 16 of the change point detection circuit 15, and the value of the out-of-synchronization output 30 changes due to the out-of-synchronization of the envelope. When the value changes from logic 0 to 1, the value is set to 4, and when the value is 7, the divided output is 2.
9 outputs a pulse to the carry output 18 and the value returns to 4, and when the value is 0, the pulse of the output 16 of the change point detection circuit 15 outputs a pulse to the carry output 19 and the value becomes 4. It returns to The operation of the pointer 24 is such that when the value of the out-of-sync output 30 changes from logical 0 to 1, the value is set to 0, the value is increased by 1 on the pulse of the output 21 of the AND gate 20, and the value is increased by 1 at the output of the AND gate 22. The value decreases by one with 23 pulses.

The above is an explanation of the operations of the reversible counter 17 and the pointer 24.

FIG. 5 shows an operation time chart of this communication speed synchronization circuit.

FIG. 5 shows a time waveform of a portion necessary for explanation in FIG. 4, where 31 indicates a time change in the value of the reversible counter 17, and T5 indicates time.

The present invention will be described in detail below with reference to FIGS. 4 and 5.

In FIG. 5, when the out-of-sync output 30 changes from logic 0 to 1 due to envelope out-of-sync, the value 31 of the reversible counter 17 and the pointer output 25 become 4 and 0, respectively.
is set to

When the pointer output 25 becomes 0, the selection circuit 26 selects the clock with the highest speed from the clock group 27 and outputs the digital phase synchronized circuit clock 3 to the digital phase synchronized circuit 2 and the frequency divider 28. do.

The frequency divider 28 divides the frequency of the digital phase-locked circuit clock 3, and the frequency division ratio here is selected so that if the clock speed is selected correctly, a divided pulse will occur twice during one envelope. . In FIG. 5, between the pulse train of the frequency divider output 29 by the digital phase synchronized circuit clock 3 selected at a certain time and the pulse train of the change point detection circuit output 16, the former has a higher frequency of pulses, and the selected clock speed It can be seen that the is large. This is detected and corrected by the reversible counter 17, which will be explained next.
The value 31 of the reversible counter 17 was set to 4 at t1, but! At T3, the pulse of the frequency divider output 29 increases by one to 5, and at T3, the output of the change point detection circuit 1
6 decreases by 1 to 4, and increases and decreases thereafter, but since the frequency of pulses of the frequency divider output 29 is higher than the frequency of pulses of the change point detection circuit output 16, the increase is greater than the decrease, and it is reversible. The value 31 of the counter 17 increases over time.

At ζ, the value 31 of the reversible counter 17 becomes 7 due to the pulse of the frequency divider output 29, and at T5, the value 31 of the reversible counter 17 becomes 7.
The pulse 9 causes a pulse at the carry output 18, and the value 31 of the reversible counter 17 returns to 4. The pulse produced at carry output 18 passes through AND gate 20 and produces a pulse at AND gate output 21 since out-of-sync output 30 is a logic one. This pulse increases the pointer output 25 by one to one. Pointer output 25
becomes 1, the clock selection circuit 26 selects from the clock group 27 the clock with the next highest speed than the previously selected clock and sets it as the digital phase synchronized circuit clock 3. This reduces the frequency of pulse generation at the frequency divider output 29.

In FIG. 5, after T5, the frequency of pulses of the change point detection circuit output 16 and the frequency of pulses of the frequency divider output 29 become equal, but this state is determined by the selection circuit 26 depending on the speed of the input transmission line 1. The digital phase synchronized circuit clock 3 is selected. At this time, since the value 31 of the reversible counter 17 is in balance with the increase and decrease, no pulse is generated in the carry output 18 and the carry output 19 unless affected by noise. If the speeds do not match, the pointer output 25 increases in the same manner as described above, and a clock with a lower speed is selected to become the digital phase synchronized circuit clock 3. It has been explained above with reference to FIG. 5 that the communication speed synchronization circuit outputs the digital phase synchronization circuit clock 3 corresponding to the speed of the input transmission line 1.

When time elapses with the digital phase synchronization circuit clock 3 of the correct speed being selected, envelope synchronization is established by the envelope synchronization circuit 6, and the synchronization is output 30.
The value becomes a logic zero, AND gates 20, 22 are closed, and pointer output 25 remains unchanged until an out-of-synchronization event occurs.

This is necessary to avoid being affected by the fact that the frequency of change points on the input transmission line 1 changes significantly when data transfer is started after envelope synchronization is established. If the number of bits of the reversible counter 17 is increased in this communication speed synchronization circuit, it will take time to synchronize the communication speed, but it will be less susceptible to noise.

Furthermore, if the pointer output 25 becomes too large due to noise or some other cause, the frequency of pulses of the change point detection circuit output 16 becomes greater than the frequency of pulses of the frequency divider output 29, contrary to the explanation described above, and the frequency of the pulses of the frequency divider output 29 becomes Counter 17 carry down output 1
A pulse at 9 causes the pointer output 25 to decrease and select the digital phase-locked circuit clock 3 according to the speed of the input transmission line 1.

Although the case where the envelope data bits are 6 bits has been described above, the present invention is not limited to this and may be used with any number of data bits.

However, in this case, it is necessary to change the frequency division ratio of the frequency divider of the communication speed synchronization circuit described above in accordance with the number of data bits so that the frequency division pulse is generated twice during one envelope. As described above, in the communication device according to the present invention, many types of communication speeds can be freely used by simply selecting the clock of the digital phase synchronization circuit of the communication device using the communication speed synchronization circuit, without changing the envelope method itself. The advantage of this method is that communication can be selectively made, eliminating the need to agree on a communication speed with the other party, and that the communication speed can be changed depending on the situation.

[Brief explanation of the drawing]

Figure 1 is a block diagram of an envelope type communication device, Figure 2 is a configuration diagram of an envelope, Figure 3 is a diagram of the bit configuration and waveform of the envelope at the time of envelope synchronization pull-in, and Figure 4 is a block diagram of the communication speed synchronization circuit. FIG. 5 is a time chart of the communication speed synchronization circuit. In the figure, 1 is the input transmission line, 2 is the digital phase synchronization circuit, 3 is the clock of the digital phase synchronization circuit, 4 is the bit clock of the input transmission line, 5 is the reception section, 6 is the envelope synchronization circuit, 7 is the transmission section, 8 is the output transmission line, 10 is the F bit, 11
is the data bit, 12 is the S bit, 13 is the envelope bit value, 15 is the change point detection circuit, 16 is the change point detection circuit output, 17 is the reversible counter, 18 is the carry output of the reversible counter, 19 is the reversible counter Downstream output, 24
is a pointer, 25 is an output indicating the value of the pointer, 26 is a clock selection circuit, 27 is a clock group, 28 is a frequency divider, 2
9 is the output of the frequency divider, 30 is the output indicating envelope synchronization loss, 38 is the reception data output, 39 is the reception control information output, 40 is the transmission data input, 41 is the transmission control information input,
Reference numeral 42 indicates a mark indicating a changing point of the input waveform, and t1 to T5 indicate times used in the explanation.

Claims (1)

[Claims] 1 In a communication method that uses an envelope composed of synchronization bits, control bits, and multiple data bits, a digital phase synchronization circuit that divides the internal clock to generate a bit clock synchronized with input bits, and a It consists of an envelope synchronization circuit that synchronizes envelopes using a synchronization bit that repeats logical "1" and "0", and a circuit that disassembles and assembles envelopes. 1. A communication device that detects a data communication speed by using the data communication speed, and automatically selects a clock to be supplied to an internal digital phase synchronization circuit according to the communication speed.