HK119597A - Method of fabricating semiconductor devices and integrated circuits using sidewall spacer technology - Google Patents

Method of fabricating semiconductor devices and integrated circuits using sidewall spacer technology

Info

Publication number
HK119597A
HK119597A HK119597A HK119597A HK119597A HK 119597 A HK119597 A HK 119597A HK 119597 A HK119597 A HK 119597A HK 119597 A HK119597 A HK 119597A HK 119597 A HK119597 A HK 119597A
Authority
HK
Hong Kong
Prior art keywords
integrated circuits
semiconductor devices
sidewall spacer
fabricating semiconductor
spacer technology
Prior art date
Application number
HK119597A
Other languages
English (en)
Inventor
Min-Liang Chen
Sailesh Chittipeddi
Taeho Kook
Richard Allyn Powell
Roy Pradip Kumar
Original Assignee
At & T Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by At & T Corp filed Critical At & T Corp
Publication of HK119597A publication Critical patent/HK119597A/xx

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158Making the insulator
    • H01L21/28167Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28176Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the definitive gate conductor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401Multistep manufacturing processes
    • H01L29/4011Multistep manufacturing processes for data storage electrodes
    • H01L29/40114Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568Lateral single gate silicon transistors
    • H01L29/66575Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B69/00Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)
  • Non-Volatile Memory (AREA)
HK119597A 1991-03-27 1997-06-26 Method of fabricating semiconductor devices and integrated circuits using sidewall spacer technology HK119597A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US67856191A 1991-03-27 1991-03-27

Publications (1)

Publication Number Publication Date
HK119597A true HK119597A (en) 1997-09-05

Family

ID=24723315

Family Applications (1)

Application Number Title Priority Date Filing Date
HK119597A HK119597A (en) 1991-03-27 1997-06-26 Method of fabricating semiconductor devices and integrated circuits using sidewall spacer technology

Country Status (8)

Country Link
US (1) US5573965A (ja)
EP (1) EP0506287B1 (ja)
JP (1) JP2644414B2 (ja)
KR (1) KR970002266B1 (ja)
DE (1) DE69217682T2 (ja)
ES (1) ES2099207T3 (ja)
HK (1) HK119597A (ja)
TW (1) TW203148B (ja)

Families Citing this family (73)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5830787A (en) * 1993-03-18 1998-11-03 Lg Semicon Co., Ltd. Method for fabricating a thin film transistor
US5716862A (en) * 1993-05-26 1998-02-10 Micron Technology, Inc. High performance PMOSFET using split-polysilicon CMOS process incorporating advanced stacked capacitior cells for fabricating multi-megabit DRAMS
US6744091B1 (en) * 1995-01-31 2004-06-01 Fujitsu Limited Semiconductor storage device with self-aligned opening and method for fabricating the same
US5858844A (en) * 1995-06-07 1999-01-12 Advanced Micro Devices, Inc. Method for construction and fabrication of submicron field-effect transistors by optimization of poly oxide process
US5907188A (en) * 1995-08-25 1999-05-25 Kabushiki Kaisha Toshiba Semiconductor device with conductive oxidation preventing film and method for manufacturing the same
US5783475A (en) * 1995-11-13 1998-07-21 Motorola, Inc. Method of forming a spacer
US5830798A (en) * 1996-01-05 1998-11-03 Micron Technology, Inc. Method for forming a field effect transistor
US5719425A (en) * 1996-01-31 1998-02-17 Micron Technology, Inc. Multiple implant lightly doped drain (MILDD) field effect transistor
US5707898A (en) * 1996-04-01 1998-01-13 Micron Technology, Inc. Method of forming a programmable non-volatile memory cell by providing a shielding layer over the gate sidewalls
US5814553A (en) * 1996-05-09 1998-09-29 United Microelectronics Corp. Method of fabricating self-align contact window with silicon nitride side wall
JP3941133B2 (ja) * 1996-07-18 2007-07-04 富士通株式会社 半導体装置およびその製造方法
US5918125A (en) * 1996-09-19 1999-06-29 Macronix International Co., Ltd. Process for manufacturing a dual floating gate oxide flash memory cell
US5904528A (en) * 1997-01-17 1999-05-18 Advanced Micro Devices, Inc. Method of forming asymmetrically doped source/drain regions
US5998274A (en) * 1997-04-10 1999-12-07 Micron Technology, Inc. Method of forming a multiple implant lightly doped drain (MILDD) field effect transistor
US6063698A (en) * 1997-06-30 2000-05-16 Motorola, Inc. Method for manufacturing a high dielectric constant gate oxide for use in semiconductor integrated circuits
KR100423577B1 (ko) * 1997-06-30 2005-05-24 주식회사 하이닉스반도체 플래쉬 메모리 소자의 제조방법
IT1293535B1 (it) * 1997-07-14 1999-03-01 Consorzio Eagle Perfezionamento nel procedimento di attacco chimico anisotropo dell'ossido di silicio, in particolare nella fabbricazione di
TW339470B (en) * 1997-09-01 1998-09-01 United Microelectronics Corp The manufacturing method for spacer
US5879993A (en) * 1997-09-29 1999-03-09 Taiwan Semiconductor Manufacturing Company, Ltd. Nitride spacer technology for flash EPROM
US5915178A (en) * 1997-12-08 1999-06-22 Taiwan Semiconductor Manufacturing Company, Ltd. Method for improving the endurance of split gate flash EEPROM devices via the addition of a shallow source side implanted region
US6001690A (en) * 1998-02-13 1999-12-14 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming flash EPROM by using iso+aniso silicon nitride spacer etching technology
US6069042A (en) * 1998-02-13 2000-05-30 Taiwan Semiconductor Manufacturing Company Multi-layer spacer technology for flash EEPROM
EP0951061A3 (en) * 1998-03-31 2003-07-09 Interuniversitair Microelektronica Centrum Vzw Method for forming a FET
JP3107157B2 (ja) * 1998-04-20 2000-11-06 日本電気株式会社 半導体装置およびその製造方法
TW377461B (en) * 1998-06-19 1999-12-21 Promos Technologies Inc Method of manufacturing gates
US6806154B1 (en) * 1998-10-08 2004-10-19 Integrated Device Technology, Inc. Method for forming a salicided MOSFET structure with tunable oxynitride spacer
WO2000030174A1 (en) * 1998-11-13 2000-05-25 Intel Corporation A method and device for improved salicide resistance on polysilicon gates
US6235598B1 (en) 1998-11-13 2001-05-22 Intel Corporation Method of using thick first spacers to improve salicide resistance on polysilicon gates
JP2000196071A (ja) * 1998-12-25 2000-07-14 Mitsubishi Electric Corp 半導体装置の製造方法及び半導体装置
DE19920333A1 (de) * 1999-05-03 2000-11-16 Siemens Ag Verfahren zur Herstellung einer Halbleitervorrichtung
US6140192A (en) * 1999-06-30 2000-10-31 United Microelectronics Corp. Method for fabricating semiconductor device
US6362062B1 (en) * 1999-09-08 2002-03-26 Texas Instruments Incorporated Disposable sidewall spacer process for integrated circuits
GB2362029A (en) * 1999-10-27 2001-11-07 Lucent Technologies Inc Multi-layer structure for MOSFET Spacers
US6251762B1 (en) 1999-12-09 2001-06-26 Intel Corporation Method and device for improved salicide resistance on polysilicon gates
US6417046B1 (en) 2000-05-05 2002-07-09 Taiwan Semiconductor Manufacturing Company Modified nitride spacer for solving charge retention issue in floating gate memory cell
US6391732B1 (en) * 2000-06-16 2002-05-21 Chartered Semiconductor Manufacturing Ltd. Method to form self-aligned, L-shaped sidewall spacers
JP3501107B2 (ja) * 2000-06-19 2004-03-02 セイコーエプソン株式会社 半導体装置の製造方法
US6468915B1 (en) * 2000-09-21 2002-10-22 Taiwan Semiconductor Manufacturing Company Method of silicon oxynitride ARC removal after gate etching
US6440875B1 (en) 2001-05-02 2002-08-27 Taiwan Semiconductor Manufacturing Co., Ltd Masking layer method for forming a spacer layer with enhanced linewidth control
JP2002353443A (ja) * 2001-05-23 2002-12-06 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
KR100411304B1 (ko) * 2001-06-30 2003-12-18 주식회사 하이닉스반도체 동기식 디램 소자의 제조방법
DE10240429A1 (de) * 2002-09-02 2004-03-18 Infineon Technologies Ag Verfahren zur Herstellung einer Halbleiterstruktur mit einer Mehrzahl von Gate-Stapeln auf einem Halbleitersubstrat und entsprechende Halbleiterstruktur
KR100482758B1 (ko) * 2002-12-12 2005-04-14 주식회사 하이닉스반도체 반도체 소자의 제조 방법
US6723638B1 (en) * 2003-02-05 2004-04-20 Advanced Micro Devices, Inc. Performance in flash memory devices
US6969646B2 (en) * 2003-02-10 2005-11-29 Chartered Semiconductor Manufacturing Ltd. Method of activating polysilicon gate structure dopants after offset spacer deposition
DE10339989B4 (de) * 2003-08-29 2008-04-17 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Herstellung eines konformen Abstandselements benachbart zu einer Gateelektrodenstruktur
US7235848B2 (en) * 2003-12-09 2007-06-26 Applied Intellectual Properties Co., Ltd. Nonvolatile memory with spacer trapping structure
US20050156229A1 (en) * 2003-12-16 2005-07-21 Yeap Geoffrey C. Integrated circuit device and method therefor
US7306995B2 (en) * 2003-12-17 2007-12-11 Texas Instruments Incorporated Reduced hydrogen sidewall spacer oxide
KR20050070627A (ko) * 2003-12-30 2005-07-07 동부아남반도체 주식회사 반도체 소자 및 그 제조방법
KR100529652B1 (ko) * 2003-12-31 2005-11-17 동부아남반도체 주식회사 반도체 장치의 제조 방법
US7112497B2 (en) * 2004-06-25 2006-09-26 Texas Instruments Incorporated Multi-layer reducible sidewall process
KR100613352B1 (ko) * 2004-12-30 2006-08-21 동부일렉트로닉스 주식회사 Rf 모스 반도체 소자의 제조 방법
US20060157750A1 (en) * 2005-01-20 2006-07-20 Samsung Electronics Co., Ltd. Semiconductor device having etch-resistant L-shaped spacer and fabrication method thereof
US7341906B2 (en) * 2005-05-19 2008-03-11 Micron Technology, Inc. Method of manufacturing sidewall spacers on a memory device, and device comprising same
US7705385B2 (en) * 2005-09-12 2010-04-27 International Business Machines Corporation Selective deposition of germanium spacers on nitride
US7994580B2 (en) 2005-10-19 2011-08-09 Taiwan Semiconductor Manufacturing Company, Ltd. High voltage transistor with improved driving current
US20070249112A1 (en) * 2006-04-21 2007-10-25 International Business Machines Corporation Differential spacer formation for a field effect transistor
KR100958620B1 (ko) * 2007-12-14 2010-05-20 주식회사 동부하이텍 반도체 소자의 제조방법
CN102299064B (zh) * 2010-06-28 2013-03-27 中芯国际集成电路制造(上海)有限公司 栅结构氧化的方法
KR101815527B1 (ko) 2010-10-07 2018-01-05 삼성전자주식회사 반도체 소자 및 그 제조 방법
FR2978294A1 (fr) * 2011-07-21 2013-01-25 St Microelectronics Rousset Procede de fabrication d'un transistor a nanocristaux
FR2978293B1 (fr) * 2011-07-21 2014-04-11 St Microelectronics Rousset Procede de fabrication d'un transistor a injection de porteurs chauds
KR101878311B1 (ko) * 2011-12-30 2018-07-17 삼성전자주식회사 high-K막을 스페이서 에치 스톱으로 이용하는 반도체 소자 형성 방법 및 관련된 소자
US9209298B2 (en) 2013-03-08 2015-12-08 Taiwan Semiconductor Manufacturing Company, Ltd. Metal-oxide-semiconductor field-effect transistor with extended gate dielectric layer
US20150200279A1 (en) * 2014-01-12 2015-07-16 United Microelectronics Corp. Method of manufacturing memory cell
US9978849B2 (en) 2015-12-29 2018-05-22 Globalfoundries Inc. SOI-MOSFET gate insulation layer with different thickness
TW201725704A (zh) * 2016-01-05 2017-07-16 聯華電子股份有限公司 非揮發性記憶體元件及其製作方法
US10270026B2 (en) * 2017-02-24 2019-04-23 Taiwan Semiconductor Manufacturing Company Ltd. Multilayered spacer structure for a magnetic tunneling junction and method of manufacturing
US10312348B1 (en) 2017-11-22 2019-06-04 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device gate spacer structures and methods thereof
US11653498B2 (en) 2017-11-30 2023-05-16 Taiwan Semiconductor Manufacturing Co., Ltd. Memory device with improved data retention
US11437493B2 (en) * 2019-01-31 2022-09-06 Taiwan Semiconductor Manufacturing Co., Ltd. Gate spacer structures and methods for forming the same
DE102020100100B4 (de) 2019-01-31 2024-06-27 Taiwan Semiconductor Manufacturing Co., Ltd. Gate-abstandshalterstrukturen und verfahren zu deren herstellung

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4038107B1 (en) * 1975-12-03 1995-04-18 Samsung Semiconductor Tele Method for making transistor structures
NL8100347A (nl) * 1981-01-26 1982-08-16 Philips Nv Halfgeleiderinrichting met een beveiligingsinrichting.
US4638347A (en) * 1982-12-07 1987-01-20 International Business Machines Corporation Gate electrode sidewall isolation spacer for field effect transistors
US4853352A (en) * 1984-07-20 1989-08-01 Lanxide Technology Company, Lp Method of making self-supporting ceramic materials and materials made thereby
US4843023A (en) * 1985-09-25 1989-06-27 Hewlett-Packard Company Process for forming lightly-doped-drain (LDD) without extra masking steps
US4735680A (en) * 1986-11-17 1988-04-05 Yen Yung Chau Method for the self-aligned silicide formation in IC fabrication
JP2608710B2 (ja) * 1986-12-29 1997-05-14 株式会社マキタ 電動工具用整流子電動機における配線装置
US4764477A (en) * 1987-04-06 1988-08-16 Motorola, Inc. CMOS process flow with small gate geometry LDO N-channel transistors
JPH0712084B2 (ja) * 1987-04-14 1995-02-08 日本電気株式会社 半導体装置の製造方法
US4786609A (en) * 1987-10-05 1988-11-22 North American Philips Corporation, Signetics Division Method of fabricating field-effect transistor utilizing improved gate sidewall spacers
US4818714A (en) * 1987-12-02 1989-04-04 Advanced Micro Devices, Inc. Method of making a high performance MOS device having LDD regions with graded junctions
US5153145A (en) * 1989-10-17 1992-10-06 At&T Bell Laboratories Fet with gate spacer
US4981810A (en) * 1990-02-16 1991-01-01 Micron Technology, Inc. Process for creating field effect transistors having reduced-slope, staircase-profile sidewall spacers
US5221632A (en) * 1990-10-31 1993-06-22 Matsushita Electric Industrial Co., Ltd. Method of proudcing a MIS transistor
JP2994128B2 (ja) * 1991-03-04 1999-12-27 シャープ株式会社 半導体装置の製造方法
KR940005293B1 (ko) * 1991-05-23 1994-06-15 삼성전자 주식회사 게이트와 드레인이 중첩된 모오스 트랜지스터의 제조방법 및 그 구조

Also Published As

Publication number Publication date
KR920018977A (ko) 1992-10-22
ES2099207T3 (es) 1997-05-16
JP2644414B2 (ja) 1997-08-25
DE69217682D1 (de) 1997-04-10
KR970002266B1 (ko) 1997-02-27
DE69217682T2 (de) 1997-09-18
EP0506287A1 (en) 1992-09-30
US5573965A (en) 1996-11-12
JPH05121732A (ja) 1993-05-18
EP0506287B1 (en) 1997-03-05
TW203148B (ja) 1993-04-01

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