FR3046874B1 - Procede de fabrication de structures semi-conductrices incluant une couche a haute resistivite, et structures semi-conductrices apparentees - Google Patents

Procede de fabrication de structures semi-conductrices incluant une couche a haute resistivite, et structures semi-conductrices apparentees Download PDF

Info

Publication number
FR3046874B1
FR3046874B1 FR1650333A FR1650333A FR3046874B1 FR 3046874 B1 FR3046874 B1 FR 3046874B1 FR 1650333 A FR1650333 A FR 1650333A FR 1650333 A FR1650333 A FR 1650333A FR 3046874 B1 FR3046874 B1 FR 3046874B1
Authority
FR
France
Prior art keywords
semiconductor structures
high resistivity
resistivity layer
manufacturing semiconductor
structures including
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR1650333A
Other languages
English (en)
Other versions
FR3046874A1 (fr
Inventor
Ionut Radu
Eric Desbonnets
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec SA filed Critical Soitec SA
Priority to FR1650333A priority Critical patent/FR3046874B1/fr
Priority to FIEP17150341.0T priority patent/FI3193361T3/fi
Priority to EP17150341.0A priority patent/EP3193361B1/fr
Priority to TW106100242A priority patent/TWI720105B/zh
Priority to JP2017003284A priority patent/JP2017126749A/ja
Priority to CN201710022513.6A priority patent/CN107068571B/zh
Priority to KR1020170006120A priority patent/KR102714466B1/ko
Priority to SG10201700308QA priority patent/SG10201700308QA/en
Priority to US15/405,867 priority patent/US10276492B2/en
Publication of FR3046874A1 publication Critical patent/FR3046874A1/fr
Application granted granted Critical
Publication of FR3046874B1 publication Critical patent/FR3046874B1/fr
Priority to JP2021125773A priority patent/JP2021168426A/ja
Priority to JP2023101912A priority patent/JP2023112087A/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238Complementary field-effect transistors, e.g. CMOS
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4803Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226Via connections in a multilevel interconnection structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76811Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving multiple stacked pre-patterned masks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76813Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving a partial via etch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816Aspects relating to the layout of the pattern or to the size of vias or trenches
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • H01L23/14Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/147Semiconductor insulating substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528Geometry or layout of the interconnection structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/58Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64Impedance arrangements
    • H01L23/66High-frequency adaptations
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64Impedance arrangements
    • H01L2223/66High-frequency adaptations
    • H01L2223/6605High-frequency electrical connections
    • H01L2223/6616Vertical connections, e.g. vias

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Recrystallisation Techniques (AREA)
  • Pressure Welding/Diffusion-Bonding (AREA)
  • Drying Of Semiconductors (AREA)
  • Semiconductor Integrated Circuits (AREA)
FR1650333A 2016-01-15 2016-01-15 Procede de fabrication de structures semi-conductrices incluant une couche a haute resistivite, et structures semi-conductrices apparentees Active FR3046874B1 (fr)

Priority Applications (11)

Application Number Priority Date Filing Date Title
FR1650333A FR3046874B1 (fr) 2016-01-15 2016-01-15 Procede de fabrication de structures semi-conductrices incluant une couche a haute resistivite, et structures semi-conductrices apparentees
FIEP17150341.0T FI3193361T3 (fi) 2016-01-15 2017-01-05 Menetelmä erittäin resistiivisen kerroksen sisältävien puolijohderakenteiden valmistamiseksi ja liittyviä puolijohderakenteita
EP17150341.0A EP3193361B1 (fr) 2016-01-15 2017-01-05 Procédé de fabrication de structures semi-conductrices incluant une couche à haute résistivité, et structures semi-conductrice apparentées
TW106100242A TWI720105B (zh) 2016-01-15 2017-01-05 用於製作包含一高電阻率層之半導體結構之方法及相關半導體結構
CN201710022513.6A CN107068571B (zh) 2016-01-15 2017-01-12 制造含高电阻率层的半导体结构的方法及相关半导体结构
JP2017003284A JP2017126749A (ja) 2016-01-15 2017-01-12 高抵抗率層を含む半導体構造を製作するための方法、および関連する半導体構造
KR1020170006120A KR102714466B1 (ko) 2016-01-15 2017-01-13 고 저항 층을 포함하는 반도체 구조들 및 관련된 반도체 구조들을 제조하기 위한 방법
SG10201700308QA SG10201700308QA (en) 2016-01-15 2017-01-13 Method For Fabricating Semiconductor Structures Including A High Resistivity Layer, And Related Semiconductor Structures
US15/405,867 US10276492B2 (en) 2016-01-15 2017-01-13 Method for fabricating semiconductor structures including a high resistivity layer, and related semiconductor structures
JP2021125773A JP2021168426A (ja) 2016-01-15 2021-07-30 高抵抗率層を含む半導体構造を製作するための方法、および関連する半導体構造
JP2023101912A JP2023112087A (ja) 2016-01-15 2023-06-21 高抵抗率層を含む半導体構造を製作するための方法、および関連する半導体構造

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1650333 2016-01-15
FR1650333A FR3046874B1 (fr) 2016-01-15 2016-01-15 Procede de fabrication de structures semi-conductrices incluant une couche a haute resistivite, et structures semi-conductrices apparentees

Publications (2)

Publication Number Publication Date
FR3046874A1 FR3046874A1 (fr) 2017-07-21
FR3046874B1 true FR3046874B1 (fr) 2018-04-13

Family

ID=55759798

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1650333A Active FR3046874B1 (fr) 2016-01-15 2016-01-15 Procede de fabrication de structures semi-conductrices incluant une couche a haute resistivite, et structures semi-conductrices apparentees

Country Status (9)

Country Link
US (1) US10276492B2 (fr)
EP (1) EP3193361B1 (fr)
JP (3) JP2017126749A (fr)
KR (1) KR102714466B1 (fr)
CN (1) CN107068571B (fr)
FI (1) FI3193361T3 (fr)
FR (1) FR3046874B1 (fr)
SG (1) SG10201700308QA (fr)
TW (1) TWI720105B (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111430217B (zh) * 2019-01-09 2022-11-29 芯恩(青岛)集成电路有限公司 一种半导体器件及其制造方法

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6154674A (ja) * 1984-08-25 1986-03-18 Fujitsu Ltd 超高周波集積回路装置
US6162665A (en) * 1993-10-15 2000-12-19 Ixys Corporation High voltage transistors and thyristors
CA2225131C (fr) * 1996-12-18 2002-01-01 Canon Kabushiki Kaisha Procede de production d'articles semi-conducteurs
JP4034099B2 (ja) * 2002-03-28 2008-01-16 株式会社ルネサステクノロジ 高周波用モノリシック集積回路装置およびその製造方法
KR20060118437A (ko) * 2003-09-26 2006-11-23 위니베르시트카솔리끄드루뱅 저항손을 감소시키는 다층 반도체 구조의 제조 방법
JP5230061B2 (ja) * 2005-07-25 2013-07-10 ラピスセミコンダクタ株式会社 半導体装置及びその製造方法
JP5367323B2 (ja) * 2008-07-23 2013-12-11 ラピスセミコンダクタ株式会社 半導体装置および半導体装置の製造方法
US9064712B2 (en) * 2010-08-12 2015-06-23 Freescale Semiconductor Inc. Monolithic microwave integrated circuit
JP2012156403A (ja) * 2011-01-27 2012-08-16 Panasonic Corp ガラス埋込シリコン基板およびその製造方法
CN102183335B (zh) * 2011-03-15 2015-10-21 迈尔森电子(天津)有限公司 Mems压力传感器及其制作方法
US8934021B2 (en) * 2012-07-02 2015-01-13 Dayton D. Eden Dual-mode terahertz imaging systems
FR2993398B1 (fr) * 2012-07-11 2015-05-29 Soitec Silicon On Insulator Structures semi-conductrices comprenant des microcanaux fluidiques pour le refroidissement et procédés associés.
US9116244B1 (en) * 2013-02-28 2015-08-25 Rockwell Collins, Inc. System for and method of weather phenomenon detection using multiple beams
CN104681562B (zh) * 2013-11-28 2017-11-14 中芯国际集成电路制造(上海)有限公司 一种集成电路及其制造方法和电子装置
US20150371905A1 (en) * 2014-06-20 2015-12-24 Rf Micro Devices, Inc. Soi with gold-doped handle wafer
US9475692B2 (en) * 2014-07-22 2016-10-25 Qorvo Us, Inc. Radio frequency (RF) microelectromechanical systems (MEMS) devices with gold-doped silicon

Also Published As

Publication number Publication date
TWI720105B (zh) 2021-03-01
JP2017126749A (ja) 2017-07-20
TW201735257A (zh) 2017-10-01
CN107068571B (zh) 2021-09-10
US10276492B2 (en) 2019-04-30
EP3193361A1 (fr) 2017-07-19
JP2023112087A (ja) 2023-08-10
SG10201700308QA (en) 2017-08-30
FI3193361T3 (fi) 2023-05-09
KR20170085981A (ko) 2017-07-25
CN107068571A (zh) 2017-08-18
EP3193361B1 (fr) 2023-04-12
KR102714466B1 (ko) 2024-10-10
JP2021168426A (ja) 2021-10-21
US20170207164A1 (en) 2017-07-20
FR3046874A1 (fr) 2017-07-21

Similar Documents

Publication Publication Date Title
FR3029682B1 (fr) Substrat semi-conducteur haute resistivite et son procede de fabrication
DE102016200026B8 (de) Wafer-Herstellungsverfahren
FR3024587B1 (fr) Procede de fabrication d'une structure hautement resistive
GB201812015D0 (en) Manufacturing method for low-temperayure polysilicon array substrate
FR3032314B1 (fr) Actionneur de positionnement et procede de fabrication
JP2017199900A5 (ja) 半導体装置の作製方法
EP3242339A4 (fr) Composition semi-conductrice organique et procédé de fabrication d'élément semi-conducteur organique
FR3042647B1 (fr) Structure composite et procede de fabrication associe
FR3026225B1 (fr) Procede de fabrication de structures semi-conductrices incluant des canaux de transistors ayant des etats de contrainte differents, et de structures semi-conductrices apparentees
FR3037438B1 (fr) Procede de fabrication d'un element semi-conducteur comprenant une couche de piegeage de charges
EP3101160A4 (fr) Procédé de fabrication de substrat de semi-conducteur
DK3548473T3 (da) HMF-fremstillingsfremgangsmåde
TWI800668B (zh) 晶片製造方法
FR3051968B1 (fr) Procede de fabrication d'un substrat semi-conducteur a haute resistivite
FR3023859B1 (fr) Element de construction isolant, procede de fabrication et materiau isolant correspondants
GB2556205B (en) Method for manufacturing thin film transistor array substrate
FR3031242B1 (fr) Procede de fabrication de nanofils ou de microfils semiconducteurs a pieds isoles
SG11201800460YA (en) Method for manufacturing semiconductor wafer
FR3041475B1 (fr) Procede de fabrication de structures pour cellule photovoltaique
EP3258512A4 (fr) Élément à semi-conducteur organique et son procédé de fabrication, composition pour former un film semi-conducteur organique et procédé de fabrication de film semi-conducteur organique
TWI800509B (zh) 器件晶片的製造方法
FR3040108B1 (fr) Procede de fabrication d'une structure semi-conductrice avec collage direct temporaire exploitant une couche poreuse
FR3050739B1 (fr) Procede de fabrication de cellules-memoires resistives
TWI800658B (zh) 晶片製造方法
FR3046874B1 (fr) Procede de fabrication de structures semi-conductrices incluant une couche a haute resistivite, et structures semi-conductrices apparentees

Legal Events

Date Code Title Description
PLFP Fee payment

Year of fee payment: 2

PLSC Publication of the preliminary search report

Effective date: 20170721

PLFP Fee payment

Year of fee payment: 3

PLFP Fee payment

Year of fee payment: 5

PLFP Fee payment

Year of fee payment: 6

PLFP Fee payment

Year of fee payment: 7

PLFP Fee payment

Year of fee payment: 8

PLFP Fee payment

Year of fee payment: 9