JP2017126749A - 高抵抗率層を含む半導体構造を製作するための方法、および関連する半導体構造 - Google Patents
高抵抗率層を含む半導体構造を製作するための方法、および関連する半導体構造 Download PDFInfo
- Publication number
- JP2017126749A JP2017126749A JP2017003284A JP2017003284A JP2017126749A JP 2017126749 A JP2017126749 A JP 2017126749A JP 2017003284 A JP2017003284 A JP 2017003284A JP 2017003284 A JP2017003284 A JP 2017003284A JP 2017126749 A JP2017126749 A JP 2017126749A
- Authority
- JP
- Japan
- Prior art keywords
- high resistivity
- substrate
- layer
- initial substrate
- semiconductor structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 65
- 239000004065 semiconductor Substances 0.000 title claims abstract description 51
- 239000000758 substrate Substances 0.000 claims abstract description 206
- 239000000463 material Substances 0.000 claims description 36
- 230000000873 masking effect Effects 0.000 claims description 28
- 238000005530 etching Methods 0.000 claims description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 8
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 7
- 229920000642 polymer Polymers 0.000 claims description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 7
- 239000000919 ceramic Substances 0.000 claims description 6
- 239000004642 Polyimide Substances 0.000 claims description 5
- 239000000853 adhesive Substances 0.000 claims description 5
- 230000001070 adhesive effect Effects 0.000 claims description 5
- 229920001721 polyimide Polymers 0.000 claims description 5
- 239000010410 layer Substances 0.000 description 128
- 238000004519 manufacturing process Methods 0.000 description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 12
- 229910052710 silicon Inorganic materials 0.000 description 11
- 239000010703 silicon Substances 0.000 description 11
- 230000015572 biosynthetic process Effects 0.000 description 9
- 238000010586 diagram Methods 0.000 description 8
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 6
- 238000003486 chemical etching Methods 0.000 description 5
- 239000007789 gas Substances 0.000 description 5
- 230000010070 molecular adhesion Effects 0.000 description 5
- 239000000126 substance Substances 0.000 description 5
- 238000004140 cleaning Methods 0.000 description 4
- 238000007790 scraping Methods 0.000 description 4
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 3
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 3
- 229910052732 germanium Inorganic materials 0.000 description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 229910052757 nitrogen Inorganic materials 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- 238000007517 polishing process Methods 0.000 description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 3
- 229910010271 silicon carbide Inorganic materials 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000003749 cleanliness Effects 0.000 description 2
- 230000006835 compression Effects 0.000 description 2
- 238000007906 compression Methods 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 238000010292 electrical insulation Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000005304 joining Methods 0.000 description 2
- 238000004377 microelectronic Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 238000009832 plasma treatment Methods 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 238000005406 washing Methods 0.000 description 2
- 238000005411 Van der Waals force Methods 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 230000003044 adaptive effect Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000000356 contaminant Substances 0.000 description 1
- 238000004320 controlled atmosphere Methods 0.000 description 1
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000000354 decomposition reaction Methods 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000032798 delamination Effects 0.000 description 1
- -1 dielectric Substances 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 230000000977 initiatory effect Effects 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 230000000644 propagated effect Effects 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76811—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving multiple stacked pre-patterned masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76813—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving a partial via etch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/147—Semiconductor insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/66—High-frequency adaptations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
- H01L2223/64—Impedance arrangements
- H01L2223/66—High-frequency adaptations
- H01L2223/6605—High-frequency electrical connections
- H01L2223/6616—Vertical connections, e.g. vias
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Recrystallisation Techniques (AREA)
- Pressure Welding/Diffusion-Bonding (AREA)
- Drying Of Semiconductors (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
− 初期基板上にデバイス層を形成するステップと、
− デバイス層の第1の面を一時的基板に取り付けるステップと、
− 高抵抗率層を形成するステップであって、高抵抗率層を形成することは初期基板の一部を除去するステップを含み、高抵抗率層は初期基板の残存部分を含む、ステップと、
− 最終基板(132、232)を高抵抗率層(136、236)に取り付けるステップと、
− 一時的基板(114、214)を除去するステップと
を含む。
・ 初期基板の一部を除去するステップは初期基板の残存部分を通って延びる複数のビア(vias)を形成するステップを含む、
・ 初期基板(102)の残存部分を通る複数のビアを形成するステップは、
・ 初期基板の残存部分の露出された面上にマスキング層を形成するステップと、
・ 初期基板のマスクされていない残存部分を通るビアをエッチングするステップと
を含む、
・ マスキング層は、複数のマスキング要素を含み、該方法は、複数のマスキング要素の総表面積を、初期基板の残存部分の露出された面の総表面積の75パーセントよりも小さくなるように選択するステップを含む、
・ 最終基板を高抵抗率層に取り付けるステップは、最終基板を複数のビアに取り付けて、最終基板とデバイス層との間に複数のキャビティ(cavities)を形成するステップを含む、
・ 方法は、複数のビア上に高抵抗率材料を形成するステップを含む、
・ 方法は、10000オームcmよりも高い電気抵抗率を有するように高抵抗率材料を選択するステップを含む、
・ 方法は、シリコン酸化物、シリコン窒化物、高抵抗率ポリマ、ポリイミド、またはセラミック接着剤(glue)のうちの少なくとも1つを含むように高抵抗率材料を選択するステップを含む。
− 最終基板と、
− 最終基板上に配置された高抵抗率層であって、高抵抗率層は初期基板の残存部分、および
− 前記残存部分を通って延びる複数のビア
を含む、高抵抗率層と、
− 高抵抗率層上に配置された無線周波数電子デバイスと
を備える半導体構造をさらに含む。
・ 高抵抗率層は、初期基板の残存部分と、複数のキャビティとを含む、
・ 高抵抗率層は、複数のビア間に配置された高抵抗率材料を含む、
・ 高抵抗率材料は、シリコン酸化物、シリコン窒化物、高抵抗率ポリマ、ポリイミド、またはセラミック接着剤のうちの1または複数を含む、
・ 高抵抗率材料は、近似的に10000オームcmよりも高い電気抵抗率を有する。
Claims (15)
- 半導体構造(140、240)を形成する方法であって、
初期基板(102)上にデバイス層(100、200)を形成するステップと、
前記デバイス層(100、200)の第1の面を一時的基板(114、214)に取り付けるステップと、
高抵抗率層(136、236)を形成するステップであって、前記高抵抗率層を形成するステップは、前記初期基板(102)の一部を除去するステップを含み、前記高抵抗率層は、前記初期基板の残存部分(102’、202’)を含む、ステップと、
最終基板(132、232)を前記高抵抗率層(136、236)に取り付けるステップと、
前記一時的基板(114、214)を除去するステップと
を含むことを特徴とする方法。 - 前記初期基板(102)の一部を除去するステップは、前記初期基板(102)の一部を薄化するステップを含むことを特徴とする請求項1に記載の方法。
- 前記初期基板(102)の一部を除去するステップは、前記初期基板(102)の残存部分(102’、202’)を通って延びる複数のビア(128、228)を形成するステップをさらに含むことを特徴とする請求項2に記載の方法。
- 前記初期基板(102)の残存部分(102’、202’)を通る複数のビア(128、228)を形成するステップは、
前記初期基板(102)の前記残存部分(102’)の露出された面(120)上にマスキング層(124)を形成するステップと、
前記初期基板(102)のマスクされていない残存部分(126)を通るビア(128)をエッチングするステップと
をさらに含むことを特徴とする請求項3に記載の方法。 - 前記マスキング層(124)は、複数のマスキング要素を含み、前記複数のマスキング要素の総表面積を、前記初期基板(102)の前記残存部分(102’)の前記露出された面(120)の総表面積の75パーセントよりも小さくなるように選択するステップをさらに含むことを特徴とする請求項4に記載の方法。
- 前記最終基板(132)を前記高抵抗率層(136)に取り付けるステップは、前記最終基板(132)を前記複数のビア(128)に取り付けて、前記最終基板(132)と前記デバイス層(100)との間に複数のキャビティ(134)を形成するステップを含むことを特徴とする請求項3ないし5のいずれかに記載の方法。
- 前記複数のビア(128、228)上に高抵抗率材料(238)を形成するステップをさらに含むことを特徴とする請求項3ないし5のいずれかに記載の方法。
- 10000オームcmよりも高い電気抵抗率を有するように前記高抵抗率材料(238)を選択するステップをさらに含むことを特徴とする請求項7に記載の方法。
- シリコン酸化物、シリコン窒化物、高抵抗率ポリマ、ポリイミド、またはセラミック接着剤のうちの少なくとも1つを含むように前記高抵抗率材料(238)を選択するステップをさらに含むことを特徴とする請求項7に記載の方法。
- 最終基板(132、232)と、
前記最終基板(132、232)上に配置された高抵抗率層(136、236)であって、前記高抵抗率層(136、236)は、初期基板(102)の残存部分(102’、202’)、および前記残存部分(102’、202’)を通って延びる複数のビア(128、228)を含む、高抵抗率層(136、236)と、
前記高抵抗率層(136、236)上に配置された無線周波数電子デバイス(100、200)と
を備えたことを特徴とする半導体構造(140、240)。 - 前記高抵抗率層(136、236)は、近似的に10000オームcmよりも高い平均電気抵抗を有する層を含むことを特徴とする請求項10に記載の半導体構造(140、240)。
- 前記高抵抗率層(136)は、前記初期基板(102)の残存部分(102’)と、複数のキャビティ(134)とを含むことを特徴とする請求項10または11に記載の半導体構造(140)。
- 前記高抵抗率層(236)は、前記複数のビア(228)間に配置された高抵抗率材料(238)をさらに含むことを特徴とする請求項10または11に記載の半導体構造(240)。
- 前記高抵抗率材料(238)は、シリコン酸化物、シリコン窒化物、高抵抗率ポリマ、ポリイミド、またはセラミック接着剤のうちの1または複数を含むことを特徴とする請求項13に記載の半導体構造(240)。
- 前記高抵抗率材料(238)は、近似的に10000オームcmよりも高い電気抵抗率を有することを特徴とする請求項13に記載の半導体構造(240)。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2021125773A JP2021168426A (ja) | 2016-01-15 | 2021-07-30 | 高抵抗率層を含む半導体構造を製作するための方法、および関連する半導体構造 |
JP2023101912A JP2023112087A (ja) | 2016-01-15 | 2023-06-21 | 高抵抗率層を含む半導体構造を製作するための方法、および関連する半導体構造 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1650333A FR3046874B1 (fr) | 2016-01-15 | 2016-01-15 | Procede de fabrication de structures semi-conductrices incluant une couche a haute resistivite, et structures semi-conductrices apparentees |
FR1650333 | 2016-01-15 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2021125773A Division JP2021168426A (ja) | 2016-01-15 | 2021-07-30 | 高抵抗率層を含む半導体構造を製作するための方法、および関連する半導体構造 |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2017126749A true JP2017126749A (ja) | 2017-07-20 |
Family
ID=55759798
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2017003284A Pending JP2017126749A (ja) | 2016-01-15 | 2017-01-12 | 高抵抗率層を含む半導体構造を製作するための方法、および関連する半導体構造 |
JP2021125773A Pending JP2021168426A (ja) | 2016-01-15 | 2021-07-30 | 高抵抗率層を含む半導体構造を製作するための方法、および関連する半導体構造 |
JP2023101912A Pending JP2023112087A (ja) | 2016-01-15 | 2023-06-21 | 高抵抗率層を含む半導体構造を製作するための方法、および関連する半導体構造 |
Family Applications After (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2021125773A Pending JP2021168426A (ja) | 2016-01-15 | 2021-07-30 | 高抵抗率層を含む半導体構造を製作するための方法、および関連する半導体構造 |
JP2023101912A Pending JP2023112087A (ja) | 2016-01-15 | 2023-06-21 | 高抵抗率層を含む半導体構造を製作するための方法、および関連する半導体構造 |
Country Status (9)
Country | Link |
---|---|
US (1) | US10276492B2 (ja) |
EP (1) | EP3193361B1 (ja) |
JP (3) | JP2017126749A (ja) |
KR (1) | KR20170085981A (ja) |
CN (1) | CN107068571B (ja) |
FI (1) | FI3193361T3 (ja) |
FR (1) | FR3046874B1 (ja) |
SG (1) | SG10201700308QA (ja) |
TW (1) | TWI720105B (ja) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111430217B (zh) * | 2019-01-09 | 2022-11-29 | 芯恩(青岛)集成电路有限公司 | 一种半导体器件及其制造方法 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6154674A (ja) * | 1984-08-25 | 1986-03-18 | Fujitsu Ltd | 超高周波集積回路装置 |
JP2003289106A (ja) * | 2002-03-28 | 2003-10-10 | Hitachi Ltd | 高周波用モノリシック集積回路装置およびその製造方法 |
CN104681562A (zh) * | 2013-11-28 | 2015-06-03 | 中芯国际集成电路制造(上海)有限公司 | 一种集成电路及其制造方法和电子装置 |
US20150371905A1 (en) * | 2014-06-20 | 2015-12-24 | Rf Micro Devices, Inc. | Soi with gold-doped handle wafer |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6162665A (en) * | 1993-10-15 | 2000-12-19 | Ixys Corporation | High voltage transistors and thyristors |
DE69728022T2 (de) * | 1996-12-18 | 2004-08-12 | Canon K.K. | Vefahren zum Herstellen eines Halbleiterartikels unter Verwendung eines Substrates mit einer porösen Halbleiterschicht |
CN1856873A (zh) * | 2003-09-26 | 2006-11-01 | 卢万天主教大学 | 制造具有降低的欧姆损耗的多层半导体结构的方法 |
JP5230061B2 (ja) * | 2005-07-25 | 2013-07-10 | ラピスセミコンダクタ株式会社 | 半導体装置及びその製造方法 |
JP5367323B2 (ja) * | 2008-07-23 | 2013-12-11 | ラピスセミコンダクタ株式会社 | 半導体装置および半導体装置の製造方法 |
US9064712B2 (en) * | 2010-08-12 | 2015-06-23 | Freescale Semiconductor Inc. | Monolithic microwave integrated circuit |
JP2012156403A (ja) * | 2011-01-27 | 2012-08-16 | Panasonic Corp | ガラス埋込シリコン基板およびその製造方法 |
CN102183335B (zh) * | 2011-03-15 | 2015-10-21 | 迈尔森电子(天津)有限公司 | Mems压力传感器及其制作方法 |
US8934021B2 (en) * | 2012-07-02 | 2015-01-13 | Dayton D. Eden | Dual-mode terahertz imaging systems |
FR2993398B1 (fr) * | 2012-07-11 | 2015-05-29 | Soitec Silicon On Insulator | Structures semi-conductrices comprenant des microcanaux fluidiques pour le refroidissement et procédés associés. |
US9116244B1 (en) * | 2013-02-28 | 2015-08-25 | Rockwell Collins, Inc. | System for and method of weather phenomenon detection using multiple beams |
US9475692B2 (en) * | 2014-07-22 | 2016-10-25 | Qorvo Us, Inc. | Radio frequency (RF) microelectromechanical systems (MEMS) devices with gold-doped silicon |
-
2016
- 2016-01-15 FR FR1650333A patent/FR3046874B1/fr active Active
-
2017
- 2017-01-05 FI FIEP17150341.0T patent/FI3193361T3/fi active
- 2017-01-05 EP EP17150341.0A patent/EP3193361B1/en active Active
- 2017-01-05 TW TW106100242A patent/TWI720105B/zh active
- 2017-01-12 CN CN201710022513.6A patent/CN107068571B/zh active Active
- 2017-01-12 JP JP2017003284A patent/JP2017126749A/ja active Pending
- 2017-01-13 KR KR1020170006120A patent/KR20170085981A/ko not_active Application Discontinuation
- 2017-01-13 SG SG10201700308QA patent/SG10201700308QA/en unknown
- 2017-01-13 US US15/405,867 patent/US10276492B2/en active Active
-
2021
- 2021-07-30 JP JP2021125773A patent/JP2021168426A/ja active Pending
-
2023
- 2023-06-21 JP JP2023101912A patent/JP2023112087A/ja active Pending
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6154674A (ja) * | 1984-08-25 | 1986-03-18 | Fujitsu Ltd | 超高周波集積回路装置 |
JP2003289106A (ja) * | 2002-03-28 | 2003-10-10 | Hitachi Ltd | 高周波用モノリシック集積回路装置およびその製造方法 |
CN104681562A (zh) * | 2013-11-28 | 2015-06-03 | 中芯国际集成电路制造(上海)有限公司 | 一种集成电路及其制造方法和电子装置 |
US20150371905A1 (en) * | 2014-06-20 | 2015-12-24 | Rf Micro Devices, Inc. | Soi with gold-doped handle wafer |
Also Published As
Publication number | Publication date |
---|---|
US10276492B2 (en) | 2019-04-30 |
KR20170085981A (ko) | 2017-07-25 |
JP2021168426A (ja) | 2021-10-21 |
TW201735257A (zh) | 2017-10-01 |
FR3046874B1 (fr) | 2018-04-13 |
TWI720105B (zh) | 2021-03-01 |
JP2023112087A (ja) | 2023-08-10 |
SG10201700308QA (en) | 2017-08-30 |
US20170207164A1 (en) | 2017-07-20 |
CN107068571A (zh) | 2017-08-18 |
EP3193361B1 (en) | 2023-04-12 |
FI3193361T3 (fi) | 2023-05-09 |
CN107068571B (zh) | 2021-09-10 |
FR3046874A1 (fr) | 2017-07-21 |
EP3193361A1 (en) | 2017-07-19 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR101292111B1 (ko) | 열팽창 계수의 국부적 적응을 갖는 헤테로구조를 제조하는 방법 | |
US5863832A (en) | Capping layer in interconnect system and method for bonding the capping layer onto the interconnect system | |
TW202002111A (zh) | 用作襯墊的直通矽穿孔 | |
KR101876912B1 (ko) | 무선 주파수 또는 전력 응용들을 위한 전자 장치 및 그와 같은 장치를 제조하는 프로세스 | |
JP5095394B2 (ja) | ウエハの移動方法 | |
EP0996150A1 (fr) | Procédé de réalisation de composants passifs et actifs sur un même substrat isolant | |
KR20070086316A (ko) | 접지면 상으로 회로를 전달하는 방법 | |
US20110076849A1 (en) | Process for bonding and transferring a layer | |
JP2014534621A (ja) | 2段階層移動方法 | |
JP2023112087A (ja) | 高抵抗率層を含む半導体構造を製作するための方法、および関連する半導体構造 | |
US10957538B2 (en) | Method of forming and transferring thin film using SOI wafer and heat treatment process | |
JP7041648B2 (ja) | 複合基板の製造方法 | |
US11315789B2 (en) | Method and structure for low density silicon oxide for fusion bonding and debonding | |
KR102568640B1 (ko) | 도너 기판의 잔류물을 제조하는 방법, 그 방법에 의해 제조된 기판 및 그 기판의 사용 | |
TWI836062B (zh) | 用於低密度矽氧化物的熔融接合與脫接方法及結構 | |
JP2023519166A (ja) | 積層構造を製造するための方法 | |
JP2005108878A (ja) | 絶縁膜の形成方法及び半導体装置の製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20191111 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20201116 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20201124 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20210224 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20210330 |