FR3040529B1 - Procede de fabrication d'une tranche soi et tranche soi - Google Patents

Procede de fabrication d'une tranche soi et tranche soi Download PDF

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Publication number
FR3040529B1
FR3040529B1 FR1657890A FR1657890A FR3040529B1 FR 3040529 B1 FR3040529 B1 FR 3040529B1 FR 1657890 A FR1657890 A FR 1657890A FR 1657890 A FR1657890 A FR 1657890A FR 3040529 B1 FR3040529 B1 FR 3040529B1
Authority
FR
France
Prior art keywords
substrate
oxide film
active layer
silicon
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR1657890A
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English (en)
French (fr)
Other versions
FR3040529A1 (enExample
Inventor
Yoshihiro Koga
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumco Corp
Original Assignee
Sumco Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumco Corp filed Critical Sumco Corp
Publication of FR3040529A1 publication Critical patent/FR3040529A1/fr
Application granted granted Critical
Publication of FR3040529B1 publication Critical patent/FR3040529B1/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H10P90/1914—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10P14/3822—
    • H10P14/6336—
    • H10P14/6682—
    • H10P14/69215—
    • H10P90/1916—
    • H10W10/181—
    • H10P50/283—
    • H10P90/1922—

Landscapes

  • Engineering & Computer Science (AREA)
  • Element Separation (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Pressure Welding/Diffusion-Bonding (AREA)
  • Formation Of Insulating Films (AREA)
FR1657890A 2015-08-27 2016-08-24 Procede de fabrication d'une tranche soi et tranche soi Active FR3040529B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2015167948A JP6471650B2 (ja) 2015-08-27 2015-08-27 Ｓｏｉウェーハの製造方法およびｓｏｉウェーハ
JP2015167948 2015-08-27

Publications (2)

Publication Number Publication Date
FR3040529A1 FR3040529A1 (enExample) 2017-03-03
FR3040529B1 true FR3040529B1 (fr) 2019-11-01

Family

ID=58018426

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1657890A Active FR3040529B1 (fr) 2015-08-27 2016-08-24 Procede de fabrication d'une tranche soi et tranche soi

Country Status (3)

Country Link
US (1) US9953859B2 (enExample)
JP (1) JP6471650B2 (enExample)
FR (1) FR3040529B1 (enExample)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6485406B2 (ja) * 2016-05-31 2019-03-20 株式会社Sumco Ｓｏｉウェーハの製造方法
CN106601615B (zh) * 2016-12-27 2020-05-15 上海新傲科技股份有限公司 提高键合强度的退火方法
TWI768957B (zh) * 2021-06-08 2022-06-21 合晶科技股份有限公司 複合基板及其製造方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3217089B2 (ja) * 1991-08-23 2001-10-09 富士通株式会社 Ｓｏｉウェハおよびその製造方法
JPH0878644A (ja) * 1994-09-02 1996-03-22 Hitachi Ltd 半導体集積回路装置の製造方法
JP2001244262A (ja) * 2000-03-02 2001-09-07 Toshiba Corp 半導体装置の製造方法
JP2006005341A (ja) * 2004-05-19 2006-01-05 Sumco Corp 貼り合わせｓｏｉ基板およびその製造方法
CN102592977B (zh) * 2007-06-20 2015-03-25 株式会社半导体能源研究所 半导体装置的制造方法
JP2009076879A (ja) * 2007-08-24 2009-04-09 Semiconductor Energy Lab Co Ltd 半導体装置
JP5365057B2 (ja) * 2008-04-11 2013-12-11 株式会社Ｓｕｍｃｏ 貼り合わせウェーハの製造方法
JP5548395B2 (ja) * 2008-06-25 2014-07-16 株式会社半導体エネルギー研究所 Ｓｏｉ基板の作製方法
JP5865057B2 (ja) * 2011-12-19 2016-02-17 株式会社半導体エネルギー研究所 半導体基板の再生方法、及びｓｏｉ基板の作製方法

Also Published As

Publication number Publication date
FR3040529A1 (enExample) 2017-03-03
JP6471650B2 (ja) 2019-02-20
US20170062267A1 (en) 2017-03-02
JP2017045885A (ja) 2017-03-02
US9953859B2 (en) 2018-04-24

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