JP6471650B2 - Soiウェーハの製造方法およびsoiウェーハ - Google Patents

Soiウェーハの製造方法およびsoiウェーハ Download PDF

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Publication number
JP6471650B2
JP6471650B2 JP2015167948A JP2015167948A JP6471650B2 JP 6471650 B2 JP6471650 B2 JP 6471650B2 JP 2015167948 A JP2015167948 A JP 2015167948A JP 2015167948 A JP2015167948 A JP 2015167948A JP 6471650 B2 JP6471650 B2 JP 6471650B2
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Prior art keywords
substrate
active layer
oxide film
soi wafer
silicon
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JP2015167948A
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Japanese (ja)
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JP2017045885A (ja
Inventor
祥泰 古賀
祥泰 古賀
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Sumco Corp
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Sumco Corp
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Priority to JP2015167948A priority Critical patent/JP6471650B2/ja
Priority to US15/241,431 priority patent/US9953859B2/en
Priority to FR1657890A priority patent/FR3040529B1/fr
Publication of JP2017045885A publication Critical patent/JP2017045885A/ja
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Publication of JP6471650B2 publication Critical patent/JP6471650B2/ja
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    • H10P90/1914
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01Manufacture or treatment
    • H10P14/3822
    • H10P14/6336
    • H10P14/6682
    • H10P14/69215
    • H10P90/1916
    • H10W10/181
    • H10P50/283
    • H10P90/1922

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  • Engineering & Computer Science (AREA)
  • Element Separation (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Pressure Welding/Diffusion-Bonding (AREA)
  • Formation Of Insulating Films (AREA)
JP2015167948A 2015-08-27 2015-08-27 Soiウェーハの製造方法およびsoiウェーハ Active JP6471650B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2015167948A JP6471650B2 (ja) 2015-08-27 2015-08-27 Soiウェーハの製造方法およびsoiウェーハ
US15/241,431 US9953859B2 (en) 2015-08-27 2016-08-19 SOI wafer manufacturing process and SOI wafer
FR1657890A FR3040529B1 (fr) 2015-08-27 2016-08-24 Procede de fabrication d'une tranche soi et tranche soi

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2015167948A JP6471650B2 (ja) 2015-08-27 2015-08-27 Soiウェーハの製造方法およびsoiウェーハ

Publications (2)

Publication Number Publication Date
JP2017045885A JP2017045885A (ja) 2017-03-02
JP6471650B2 true JP6471650B2 (ja) 2019-02-20

Family

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JP2015167948A Active JP6471650B2 (ja) 2015-08-27 2015-08-27 Soiウェーハの製造方法およびsoiウェーハ

Country Status (3)

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US (1) US9953859B2 (enExample)
JP (1) JP6471650B2 (enExample)
FR (1) FR3040529B1 (enExample)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6485406B2 (ja) * 2016-05-31 2019-03-20 株式会社Sumco Soiウェーハの製造方法
CN106601615B (zh) * 2016-12-27 2020-05-15 上海新傲科技股份有限公司 提高键合强度的退火方法
TWI768957B (zh) * 2021-06-08 2022-06-21 合晶科技股份有限公司 複合基板及其製造方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3217089B2 (ja) * 1991-08-23 2001-10-09 富士通株式会社 Soiウェハおよびその製造方法
JPH0878644A (ja) * 1994-09-02 1996-03-22 Hitachi Ltd 半導体集積回路装置の製造方法
JP2001244262A (ja) * 2000-03-02 2001-09-07 Toshiba Corp 半導体装置の製造方法
JP2006005341A (ja) * 2004-05-19 2006-01-05 Sumco Corp 貼り合わせsoi基板およびその製造方法
CN102592977B (zh) * 2007-06-20 2015-03-25 株式会社半导体能源研究所 半导体装置的制造方法
JP2009076879A (ja) * 2007-08-24 2009-04-09 Semiconductor Energy Lab Co Ltd 半導体装置
JP5365057B2 (ja) * 2008-04-11 2013-12-11 株式会社Sumco 貼り合わせウェーハの製造方法
JP5548395B2 (ja) * 2008-06-25 2014-07-16 株式会社半導体エネルギー研究所 Soi基板の作製方法
JP5865057B2 (ja) * 2011-12-19 2016-02-17 株式会社半導体エネルギー研究所 半導体基板の再生方法、及びsoi基板の作製方法

Also Published As

Publication number Publication date
FR3040529A1 (enExample) 2017-03-03
FR3040529B1 (fr) 2019-11-01
US20170062267A1 (en) 2017-03-02
JP2017045885A (ja) 2017-03-02
US9953859B2 (en) 2018-04-24

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