FR2433223A1 - Circuit de lecture/ecriture pour une memoire - Google Patents

Circuit de lecture/ecriture pour une memoire

Info

Publication number
FR2433223A1
FR2433223A1 FR7920223A FR7920223A FR2433223A1 FR 2433223 A1 FR2433223 A1 FR 2433223A1 FR 7920223 A FR7920223 A FR 7920223A FR 7920223 A FR7920223 A FR 7920223A FR 2433223 A1 FR2433223 A1 FR 2433223A1
Authority
FR
France
Prior art keywords
read
write circuit
memory
during
decoders
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7920223A
Other languages
English (en)
Other versions
FR2433223B1 (fr
Inventor
Andrew Gordon Francis Dingwall
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
RCA Corp
Original Assignee
RCA Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by RCA Corp filed Critical RCA Corp
Publication of FR2433223A1 publication Critical patent/FR2433223A1/fr
Application granted granted Critical
Publication of FR2433223B1 publication Critical patent/FR2433223B1/fr
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/418—Address circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)

Abstract

L'invention concerne les mémoires. Un circuit de lecture/écriture associé à un réseau 7 de cellules de mémoire 8 comprend notamment un multiplicateur de tension 12 et des décodeurs à décalage de niveau D1 ... Dn . Le multiplicateur de tension applique des tensions différentes aux décodeurs pendant un cycle de lecture et pendant un cycle d'écriture, pour éviter toute écriture erronée, tout en assurant une lecture non destructive. Application aux mémoires à semi-conducteurs.
FR7920223A 1978-08-07 1979-08-07 Circuit de lecture/ecriture pour une memoire Expired FR2433223B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/931,530 US4189782A (en) 1978-08-07 1978-08-07 Memory organization

Publications (2)

Publication Number Publication Date
FR2433223A1 true FR2433223A1 (fr) 1980-03-07
FR2433223B1 FR2433223B1 (fr) 1985-11-22

Family

ID=25460924

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7920223A Expired FR2433223B1 (fr) 1978-08-07 1979-08-07 Circuit de lecture/ecriture pour une memoire

Country Status (6)

Country Link
US (1) US4189782A (fr)
JP (1) JPS5821359B2 (fr)
DE (1) DE2932020C2 (fr)
FR (1) FR2433223B1 (fr)
GB (1) GB2028046B (fr)
IT (1) IT1122305B (fr)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4724530A (en) * 1978-10-03 1988-02-09 Rca Corporation Five transistor CMOS memory cell including diodes
JPS5597734A (en) * 1979-01-19 1980-07-25 Toshiba Corp Logic circuit
US4281400A (en) * 1979-12-28 1981-07-28 Rca Corporation Circuit for reducing the loading effect of an insulated-gate field-effect transistor (IGFET) on a signal source
US4463318A (en) * 1982-08-30 1984-07-31 Rca Corporation Power amplifier circuit employing field-effect power transistors
US4506349A (en) * 1982-12-20 1985-03-19 General Electric Company Cross-coupled transistor memory cell for MOS random access memory of reduced power dissipation
US4499558A (en) * 1983-02-04 1985-02-12 General Electric Company Five-transistor static memory cell implemental in CMOS/bulk
JPS59191648A (ja) * 1983-04-14 1984-10-30 Sanyo Electric Co Ltd コ−ド検出回路
JPS60158459U (ja) * 1984-03-30 1985-10-22 フランスベッド株式会社 マツトレス装置
JPS6238592A (ja) * 1985-08-14 1987-02-19 Fujitsu Ltd 相補型メモリの行選択線駆動回路
US5051959A (en) * 1985-08-14 1991-09-24 Fujitsu Limited Complementary semiconductor memory device including cell access transistor and word line driving transistor having channels of different conductivity type
US4821233A (en) * 1985-09-19 1989-04-11 Xilinx, Incorporated 5-transistor memory cell with known state on power-up
US4750155A (en) * 1985-09-19 1988-06-07 Xilinx, Incorporated 5-Transistor memory cell which can be reliably read and written
JPS62136919A (ja) * 1985-12-10 1987-06-19 Mitsubishi Electric Corp ドライバ−回路
JPS63104290A (ja) * 1986-10-21 1988-05-09 Nec Corp 半導体記憶装置
JPS63146559U (fr) * 1987-03-18 1988-09-27
JP3228759B2 (ja) * 1990-01-24 2001-11-12 セイコーエプソン株式会社 半導体記憶装置及びデータ処理装置
GB2243233A (en) * 1990-04-06 1991-10-23 Mosaid Inc DRAM word line driver
GB9007791D0 (en) * 1990-04-06 1990-06-06 Foss Richard C High voltage boosted wordline supply charge pump and regulator for dram
US5751643A (en) * 1990-04-06 1998-05-12 Mosaid Technologies Incorporated Dynamic memory word line driver
GB9007790D0 (en) * 1990-04-06 1990-06-06 Lines Valerie L Dynamic memory wordline driver scheme
JPH0878433A (ja) * 1994-08-31 1996-03-22 Nec Corp 半導体装置
US5784313A (en) * 1995-08-18 1998-07-21 Xilinx, Inc. Programmable logic device including configuration data or user data memory slices
US10985162B2 (en) * 2018-12-14 2021-04-20 John Bennett System for accurate multiple level gain cells

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3521242A (en) * 1967-05-02 1970-07-21 Rca Corp Complementary transistor write and ndro for memory cell
US4063225A (en) * 1976-03-08 1977-12-13 Rca Corporation Memory cell and array
US4095282A (en) * 1976-11-23 1978-06-13 Westinghouse Electric Corp. Memory including varactor circuit to boost address signals
US4156940A (en) * 1978-03-27 1979-05-29 Rca Corporation Memory array with bias voltage generator

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1504867A (en) * 1974-06-05 1978-03-22 Rca Corp Voltage amplitude multiplying circuits

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3521242A (en) * 1967-05-02 1970-07-21 Rca Corp Complementary transistor write and ndro for memory cell
US4063225A (en) * 1976-03-08 1977-12-13 Rca Corporation Memory cell and array
US4095282A (en) * 1976-11-23 1978-06-13 Westinghouse Electric Corp. Memory including varactor circuit to boost address signals
US4156940A (en) * 1978-03-27 1979-05-29 Rca Corporation Memory array with bias voltage generator

Also Published As

Publication number Publication date
IT1122305B (it) 1986-04-23
DE2932020C2 (de) 1982-04-29
FR2433223B1 (fr) 1985-11-22
JPS5525895A (en) 1980-02-23
GB2028046A (en) 1980-02-27
US4189782A (en) 1980-02-19
GB2028046B (en) 1982-08-25
DE2932020A1 (de) 1980-02-14
JPS5821359B2 (ja) 1983-04-28
IT7924609A0 (it) 1979-07-24

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Legal Events

Date Code Title Description
ST Notification of lapse