IT7924609A0 - Organizzazione di una memoria. - Google Patents

Organizzazione di una memoria.

Info

Publication number
IT7924609A0
IT7924609A0 IT7924609A IT2460979A IT7924609A0 IT 7924609 A0 IT7924609 A0 IT 7924609A0 IT 7924609 A IT7924609 A IT 7924609A IT 2460979 A IT2460979 A IT 2460979A IT 7924609 A0 IT7924609 A0 IT 7924609A0
Authority
IT
Italy
Prior art keywords
organization
memory
Prior art date
Application number
IT7924609A
Other languages
English (en)
Other versions
IT1122305B (it
Original Assignee
Rca Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rca Corp filed Critical Rca Corp
Publication of IT7924609A0 publication Critical patent/IT7924609A0/it
Application granted granted Critical
Publication of IT1122305B publication Critical patent/IT1122305B/it

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/418—Address circuits
IT24609/79A 1978-08-07 1979-07-24 Organizzazione di una memoria IT1122305B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/931,530 US4189782A (en) 1978-08-07 1978-08-07 Memory organization

Publications (2)

Publication Number Publication Date
IT7924609A0 true IT7924609A0 (it) 1979-07-24
IT1122305B IT1122305B (it) 1986-04-23

Family

ID=25460924

Family Applications (1)

Application Number Title Priority Date Filing Date
IT24609/79A IT1122305B (it) 1978-08-07 1979-07-24 Organizzazione di una memoria

Country Status (6)

Country Link
US (1) US4189782A (it)
JP (1) JPS5821359B2 (it)
DE (1) DE2932020C2 (it)
FR (1) FR2433223B1 (it)
GB (1) GB2028046B (it)
IT (1) IT1122305B (it)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4724530A (en) * 1978-10-03 1988-02-09 Rca Corporation Five transistor CMOS memory cell including diodes
JPS5597734A (en) * 1979-01-19 1980-07-25 Toshiba Corp Logic circuit
US4281400A (en) * 1979-12-28 1981-07-28 Rca Corporation Circuit for reducing the loading effect of an insulated-gate field-effect transistor (IGFET) on a signal source
US4463318A (en) * 1982-08-30 1984-07-31 Rca Corporation Power amplifier circuit employing field-effect power transistors
US4506349A (en) * 1982-12-20 1985-03-19 General Electric Company Cross-coupled transistor memory cell for MOS random access memory of reduced power dissipation
US4499558A (en) * 1983-02-04 1985-02-12 General Electric Company Five-transistor static memory cell implemental in CMOS/bulk
JPS59191648A (ja) * 1983-04-14 1984-10-30 Sanyo Electric Co Ltd コ−ド検出回路
JPS60158459U (ja) * 1984-03-30 1985-10-22 フランスベッド株式会社 マツトレス装置
US5051959A (en) * 1985-08-14 1991-09-24 Fujitsu Limited Complementary semiconductor memory device including cell access transistor and word line driving transistor having channels of different conductivity type
JPS6238592A (ja) * 1985-08-14 1987-02-19 Fujitsu Ltd 相補型メモリの行選択線駆動回路
US4750155A (en) * 1985-09-19 1988-06-07 Xilinx, Incorporated 5-Transistor memory cell which can be reliably read and written
US4821233A (en) * 1985-09-19 1989-04-11 Xilinx, Incorporated 5-transistor memory cell with known state on power-up
JPS62136919A (ja) * 1985-12-10 1987-06-19 Mitsubishi Electric Corp ドライバ−回路
JPS63104290A (ja) * 1986-10-21 1988-05-09 Nec Corp 半導体記憶装置
JPS63146559U (it) * 1987-03-18 1988-09-27
JP3228759B2 (ja) * 1990-01-24 2001-11-12 セイコーエプソン株式会社 半導体記憶装置及びデータ処理装置
US5751643A (en) * 1990-04-06 1998-05-12 Mosaid Technologies Incorporated Dynamic memory word line driver
GB9007790D0 (en) 1990-04-06 1990-06-06 Lines Valerie L Dynamic memory wordline driver scheme
US5214602A (en) * 1990-04-06 1993-05-25 Mosaid Inc. Dynamic memory word line driver scheme
GB9007791D0 (en) 1990-04-06 1990-06-06 Foss Richard C High voltage boosted wordline supply charge pump and regulator for dram
JPH0878433A (ja) * 1994-08-31 1996-03-22 Nec Corp 半導体装置
US5784313A (en) 1995-08-18 1998-07-21 Xilinx, Inc. Programmable logic device including configuration data or user data memory slices
US10985162B2 (en) * 2018-12-14 2021-04-20 John Bennett System for accurate multiple level gain cells

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3521242A (en) * 1967-05-02 1970-07-21 Rca Corp Complementary transistor write and ndro for memory cell
GB1504867A (en) * 1974-06-05 1978-03-22 Rca Corp Voltage amplitude multiplying circuits
US4063225A (en) * 1976-03-08 1977-12-13 Rca Corporation Memory cell and array
US4095282A (en) * 1976-11-23 1978-06-13 Westinghouse Electric Corp. Memory including varactor circuit to boost address signals
US4156940A (en) * 1978-03-27 1979-05-29 Rca Corporation Memory array with bias voltage generator

Also Published As

Publication number Publication date
GB2028046B (en) 1982-08-25
JPS5525895A (en) 1980-02-23
FR2433223A1 (fr) 1980-03-07
US4189782A (en) 1980-02-19
DE2932020A1 (de) 1980-02-14
FR2433223B1 (fr) 1985-11-22
DE2932020C2 (de) 1982-04-29
GB2028046A (en) 1980-02-27
JPS5821359B2 (ja) 1983-04-28
IT1122305B (it) 1986-04-23

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