FR2400747A1 - Matrice a semi-conducteurs pour memoire permanente a circuits integres - Google Patents
Matrice a semi-conducteurs pour memoire permanente a circuits integresInfo
- Publication number
- FR2400747A1 FR2400747A1 FR7823872A FR7823872A FR2400747A1 FR 2400747 A1 FR2400747 A1 FR 2400747A1 FR 7823872 A FR7823872 A FR 7823872A FR 7823872 A FR7823872 A FR 7823872A FR 2400747 A1 FR2400747 A1 FR 2400747A1
- Authority
- FR
- France
- Prior art keywords
- conductivity type
- semiconductor
- bars
- elements
- permanent memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title abstract 5
- 239000011159 matrix material Substances 0.000 title abstract 3
- 239000002184 metal Substances 0.000 abstract 3
- 239000000758 substrate Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/102—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including bipolar components
- H01L27/1021—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including bipolar components including diodes only
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/08—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/456—Ohmic electrodes on silicon
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/055—Fuse
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
- Read Only Memory (AREA)
Abstract
Matrice à semi-conducteurs pour mémoire permanente intégrée, composée d'éléments comportant une région d'un premier type de conductivité, dans lequel, au moins dans une partie des éléments, une région 5 du second type de conductivité étant prévue dans au moins une partie de ces éléments, ceux-ci étant formés à l'intersection de barres semi-conductrices 2 du premier type de conductivité réalisées dans le substrat, et de barres métalliques 3 disposées sur une couche diélectrique 4 qui isole les barres semi-conductrices des barres métalliques, des fenêtres étant prévues dans la couche diélectrique au-dessus des régions 5 du second type de conductivité, au moins une partie de ces fenêtres comportant des ouvertures 6 assurant le contact électrique entre les régions semi-conductrices 5 du second type de conductivité avec les barres métalliques, ladite matrice étant caractérisée en ce que les régions 5 du second type de conductivité ne sont associées qu'aux éléments, au-dessus desquels sont pratiquées des ouvertures 6, dans la couche diélectrique 4, ces dernieres coïncidant avec les fenêtres.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
SU2517209 | 1977-08-16 |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2400747A1 true FR2400747A1 (fr) | 1979-03-16 |
FR2400747B1 FR2400747B1 (fr) | 1984-11-23 |
Family
ID=20721981
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR7823872A Granted FR2400747A1 (fr) | 1977-08-16 | 1978-08-16 | Matrice a semi-conducteurs pour memoire permanente a circuits integres |
Country Status (5)
Country | Link |
---|---|
US (1) | US4195354A (fr) |
JP (1) | JPS5448453A (fr) |
DE (1) | DE2835087C2 (fr) |
FR (1) | FR2400747A1 (fr) |
GB (1) | GB2004688B (fr) |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3721964A (en) * | 1970-02-18 | 1973-03-20 | Hewlett Packard Co | Integrated circuit read only memory bit organized in coincident select structure |
US3717852A (en) * | 1971-09-17 | 1973-02-20 | Ibm | Electronically rewritable read-only memory using via connections |
GB1357515A (en) * | 1972-03-10 | 1974-06-26 | Matsushita Electronics Corp | Method for manufacturing an mos integrated circuit |
JPS5416990A (en) * | 1977-07-08 | 1979-02-07 | Hitachi Ltd | Matrix form logic circuit |
-
1978
- 1978-08-07 US US05/931,422 patent/US4195354A/en not_active Expired - Lifetime
- 1978-08-10 DE DE2835087A patent/DE2835087C2/de not_active Expired
- 1978-08-16 GB GB7833605A patent/GB2004688B/en not_active Expired
- 1978-08-16 FR FR7823872A patent/FR2400747A1/fr active Granted
- 1978-08-16 JP JP9918378A patent/JPS5448453A/ja active Pending
Also Published As
Publication number | Publication date |
---|---|
GB2004688B (en) | 1982-05-06 |
GB2004688A (en) | 1979-04-04 |
DE2835087C2 (de) | 1984-10-31 |
FR2400747B1 (fr) | 1984-11-23 |
DE2835087A1 (de) | 1979-03-01 |
JPS5448453A (en) | 1979-04-17 |
US4195354A (en) | 1980-03-25 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
ST | Notification of lapse |