FR2365857A1 - Structure de memoire serie a lecture seule - Google Patents

Structure de memoire serie a lecture seule

Info

Publication number
FR2365857A1
FR2365857A1 FR7722453A FR7722453A FR2365857A1 FR 2365857 A1 FR2365857 A1 FR 2365857A1 FR 7722453 A FR7722453 A FR 7722453A FR 7722453 A FR7722453 A FR 7722453A FR 2365857 A1 FR2365857 A1 FR 2365857A1
Authority
FR
France
Prior art keywords
transistors
read
drain
source
inputs
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7722453A
Other languages
English (en)
Other versions
FR2365857B1 (fr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CTU of Delaware Inc
Original Assignee
Mostek Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mostek Corp filed Critical Mostek Corp
Publication of FR2365857A1 publication Critical patent/FR2365857A1/fr
Application granted granted Critical
Publication of FR2365857B1 publication Critical patent/FR2365857B1/fr
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/08—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements
    • G11C17/10—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM
    • G11C17/12—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM using field-effect devices
    • G11C17/123—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM using field-effect devices comprising cells having several storage transistors connected in series
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • H03K19/1776—Structural details of configuration resources for memories
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/1778—Structural details for adapting physical parameters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/1778—Structural details for adapting physical parameters
    • H03K19/17796—Structural details for adapting physical parameters for physical disposition of blocks

Abstract

a. Structure de matrice logique. b. Structure caractérisée en ce qu'elle comprend un substrat semi-conducteur, une matrice d'élements de transistors à effet de champ à grille isolée placés en des points prédéterminés du substrat, chacun de ces éléments de transistor présentant différentes parties définissant une grille, une source, un drain et une région de canal entre la source et le drain, chaque élément de transistor étant placé dans la matrice de manière à définir un certain nombre de rangées d'entrées et de colonnes de sorties, les grilles des transistors de chaque rangée d'entrées étant branchées électriquement en commun, et les drains des transistors de chaque colonne étant branchés en série avec les sources des transistors adjacents dans celle-ci. des mémoires à c. L'invention s'applique dans le domaine des mémoires à lecture seule pour traitement de données logiques.
FR7722453A 1976-09-27 1977-07-21 Structure de memoire serie a lecture seule Granted FR2365857A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/726,579 US4142176A (en) 1976-09-27 1976-09-27 Series read only memory structure

Publications (2)

Publication Number Publication Date
FR2365857A1 true FR2365857A1 (fr) 1978-04-21
FR2365857B1 FR2365857B1 (fr) 1984-07-06

Family

ID=24919173

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7722453A Granted FR2365857A1 (fr) 1976-09-27 1977-07-21 Structure de memoire serie a lecture seule

Country Status (6)

Country Link
US (1) US4142176A (fr)
JP (2) JPS5341951A (fr)
DE (1) DE2731873A1 (fr)
FR (1) FR2365857A1 (fr)
GB (1) GB1556108A (fr)
IT (1) IT1079409B (fr)

Families Citing this family (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4202044A (en) * 1978-06-13 1980-05-06 International Business Machines Corporation Quaternary FET read only memory
USRE32401E (en) * 1978-06-13 1987-04-14 International Business Machines Corporation Quaternary FET read only memory
JPS5843838B2 (ja) * 1979-02-28 1983-09-29 富士通株式会社 読取り専用メモリ
US4274147A (en) * 1979-09-04 1981-06-16 Rockwell International Corporation Static read only memory
JPS5650630A (en) * 1979-10-01 1981-05-07 Mitsubishi Electric Corp Semiconductor integrated circuit
US4602354A (en) * 1983-01-10 1986-07-22 Ncr Corporation X-and-OR memory array
US4570239A (en) * 1983-01-24 1986-02-11 Motorola, Inc. Series read-only-memory having capacitive bootstrap precharging circuitry
US5184202A (en) * 1983-07-27 1993-02-02 Hitachi, Ltd. Semiconductor integrated circuit device
JPH073862B2 (ja) * 1983-07-27 1995-01-18 株式会社日立製作所 半導体記憶装置
DE3831538C2 (de) * 1987-09-18 1996-03-28 Toshiba Kawasaki Kk Elektrisch löschbare und programmierbare Halbleiter-Speichervorrichtung
US5198996A (en) * 1988-05-16 1993-03-30 Matsushita Electronics Corporation Semiconductor non-volatile memory device
DE68916855T2 (de) * 1988-05-16 1995-01-19 Matsushita Electronics Corp Nichtflüchtige Halbleiterspeicheranordnung.
CA1309781C (fr) * 1988-06-21 1992-11-03 Colin Harris Matrice de commutation analogique compacte a cmos
KR940008703Y1 (ko) * 1989-05-09 1994-12-27 삼성전자 주식회사 멀티 시스템의 모우드 절환시 노이즈 제거회로
US5200355A (en) * 1990-12-10 1993-04-06 Samsung Electronics Co., Ltd. Method for manufacturing a mask read only memory device
JP3109537B2 (ja) * 1991-07-12 2000-11-20 日本電気株式会社 読み出し専用半導体記憶装置
FR2730345B1 (fr) * 1995-02-03 1997-04-04 Matra Mhs Procede de fabrication d'une memoire morte en technologie mos, et memoire ainsi obtenue
JPH09161495A (ja) * 1995-12-12 1997-06-20 Ricoh Co Ltd 半導体メモリ装置
US6137318A (en) * 1997-12-09 2000-10-24 Oki Electric Industry Co., Ltd. Logic circuit having dummy MOS transistor
EP1126614B1 (fr) * 2000-02-14 2004-11-17 STMicroelectronics S.r.l. Réseaux logiques programmables
US6512694B2 (en) 2001-03-16 2003-01-28 Simtek Corporation NAND stack EEPROM with random programming capability
US6414873B1 (en) 2001-03-16 2002-07-02 Simtek Corporation nvSRAM with multiple non-volatile memory cells for each SRAM memory cell
US7005711B2 (en) * 2002-12-20 2006-02-28 Progressant Technologies, Inc. N-channel pull-up element and logic circuit
US7505321B2 (en) * 2002-12-31 2009-03-17 Sandisk 3D Llc Programmable memory array structure incorporating series-connected transistor strings and methods for fabrication and operation of same
US7005350B2 (en) * 2002-12-31 2006-02-28 Matrix Semiconductor, Inc. Method for fabricating programmable memory array structures incorporating series-connected transistor strings
US7233522B2 (en) * 2002-12-31 2007-06-19 Sandisk 3D Llc NAND memory array incorporating capacitance boosting of channel regions in unselected memory cells and method for operation of same
US20050128807A1 (en) * 2003-12-05 2005-06-16 En-Hsing Chen Nand memory array incorporating multiple series selection devices and method for operation of same
US7023739B2 (en) * 2003-12-05 2006-04-04 Matrix Semiconductor, Inc. NAND memory array incorporating multiple write pulse programming of individual memory cells and method for operation of same
US7221588B2 (en) * 2003-12-05 2007-05-22 Sandisk 3D Llc Memory array incorporating memory cells arranged in NAND strings
CN101336417A (zh) * 2005-11-25 2008-12-31 诺韦利克斯有限责任公司 致密只读存储器
US20080151654A1 (en) 2006-12-22 2008-06-26 Allan James D Method and apparatus to implement a reset function in a non-volatile static random access memory

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3728696A (en) * 1971-12-23 1973-04-17 North American Rockwell High density read-only memory

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3405399A (en) * 1964-06-16 1968-10-08 Sperry Rand Corp Matrix selection circuit
US3613055A (en) * 1969-12-23 1971-10-12 Andrew G Varadi Read-only memory utilizing service column switching techniques
GB1357515A (en) * 1972-03-10 1974-06-26 Matsushita Electronics Corp Method for manufacturing an mos integrated circuit
JPS4945177A (fr) * 1972-09-05 1974-04-30
DE2264287C2 (de) * 1972-12-30 1975-02-27 Deutsche Texaco Ag, 2000 Hamburg Verfahren zur Herstellung und/oder Härtung von Polykondensationsharzen
JPS5751195B2 (fr) * 1974-07-03 1982-10-30
JPS5185640A (fr) * 1975-01-25 1976-07-27 Nippon Electric Co
JPS51111020A (en) * 1975-03-26 1976-10-01 Hitachi Ltd Semiconductor fixing memory equipment
US4059826A (en) * 1975-12-29 1977-11-22 Texas Instruments Incorporated Semiconductor memory array with field effect transistors programmable by alteration of threshold voltage

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3728696A (en) * 1971-12-23 1973-04-17 North American Rockwell High density read-only memory

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
EXBK/73 *
EXBK/76 *

Also Published As

Publication number Publication date
DE2731873A1 (de) 1978-03-30
JPS5890599U (ja) 1983-06-18
US4142176A (en) 1979-02-27
JPS5341951A (en) 1978-04-15
JPS6041040Y2 (ja) 1985-12-12
DE2731873C2 (fr) 1987-01-02
GB1556108A (en) 1979-11-21
IT1079409B (it) 1985-05-13
FR2365857B1 (fr) 1984-07-06

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