FR2390003A1 - - Google Patents
Info
- Publication number
- FR2390003A1 FR2390003A1 FR7810335A FR7810335A FR2390003A1 FR 2390003 A1 FR2390003 A1 FR 2390003A1 FR 7810335 A FR7810335 A FR 7810335A FR 7810335 A FR7810335 A FR 7810335A FR 2390003 A1 FR2390003 A1 FR 2390003A1
- Authority
- FR
- France
- Prior art keywords
- silicon
- silicide
- mask
- deposited
- metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 4
- 229910021332 silicide Inorganic materials 0.000 abstract 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 abstract 3
- 229910052710 silicon Inorganic materials 0.000 abstract 3
- 239000010703 silicon Substances 0.000 abstract 3
- 239000002184 metal Substances 0.000 abstract 2
- 230000000295 complement effect Effects 0.000 abstract 1
- 230000008021 deposition Effects 0.000 abstract 1
- 230000005669 field effect Effects 0.000 abstract 1
- 238000010438 heat treatment Methods 0.000 abstract 1
- 238000004519 manufacturing process Methods 0.000 abstract 1
- 238000005272 metallurgy Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
- 239000004065 semiconductor Substances 0.000 abstract 1
- 239000000758 substrate Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0272—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers for lift-off processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28525—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising semiconducting material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
- H01L21/86—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body the insulating body being sapphire, e.g. silicon on sapphire structure, i.e. SOS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4941—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a barrier layer between the silicon and the metal or metal silicide upper layer, e.g. Silicide/TiN/Polysilicon
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/103—Mask, dual function, e.g. diffusion and oxidation
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/141—Self-alignment coat gate
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/147—Silicides
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/942—Masking
- Y10S438/948—Radiation resist
- Y10S438/951—Lift-off
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Procédé de fabrication de transistors à effet de champ à porte isolée en silicium et munis de contacts en siliciure. Ce procédé comprend d'abord le dépôt d'un métal 7 susceptible de former un siliciure sur la région source ou drain 2 d'un transistor MOSFET grâce à une première étape photolithographique. Puis grâce à une deuxième étape photolithographique (masque 4a), on dépose une couche de silicium 9. A travers les ouvertures du masque 4a, le silicium forme l'électrode de porte du MOSFET et vient en contact avec le métal 7. On dépose une métallurgie complémentaire, par exemple Cr-A2/Cu 12, 14 à travers le même masque, ce dernier est éliminé. On procède alors à une étape de chauffage pour former le siliciure, entre les couches 7 et 9 et éventuellement 2 si le substrat 1 est en silicium. Application à l'industrie de circuits intégrés à semi-conducteurs.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US05/793,231 US4109372A (en) | 1977-05-02 | 1977-05-02 | Method for making an insulated gate field effect transistor utilizing a silicon gate and silicide interconnection vias |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2390003A1 true FR2390003A1 (fr) | 1978-12-01 |
FR2390003B1 FR2390003B1 (fr) | 1980-08-29 |
Family
ID=25159441
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR7810335A Expired FR2390003B1 (fr) | 1977-05-02 | 1978-03-31 |
Country Status (5)
Country | Link |
---|---|
US (1) | US4109372A (fr) |
JP (1) | JPS53136488A (fr) |
DE (1) | DE2817258A1 (fr) |
FR (1) | FR2390003B1 (fr) |
GB (1) | GB1562877A (fr) |
Families Citing this family (27)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
NL190710C (nl) * | 1978-02-10 | 1994-07-01 | Nec Corp | Geintegreerde halfgeleiderketen. |
NL7902247A (nl) * | 1978-03-25 | 1979-09-27 | Fujitsu Ltd | Metaal-isolator-halfgeleidertype halfgeleiderinrich- ting en werkwijze voor het vervaardigen ervan. |
JPS55138874A (en) * | 1979-04-18 | 1980-10-30 | Fujitsu Ltd | Semiconductor device and method of fabricating the same |
US4228212A (en) * | 1979-06-11 | 1980-10-14 | General Electric Company | Composite conductive structures in integrated circuits |
US4227944A (en) * | 1979-06-11 | 1980-10-14 | General Electric Company | Methods of making composite conductive structures in integrated circuits |
US4263058A (en) * | 1979-06-11 | 1981-04-21 | General Electric Company | Composite conductive structures in integrated circuits and method of making same |
JPS5927102B2 (ja) * | 1979-12-24 | 1984-07-03 | 富士通株式会社 | 半導体記憶装置 |
US4276688A (en) * | 1980-01-21 | 1981-07-07 | Rca Corporation | Method for forming buried contact complementary MOS devices |
US4301588A (en) * | 1980-02-01 | 1981-11-24 | International Business Machines Corporation | Consumable amorphous or polysilicon emitter process |
US4343082A (en) * | 1980-04-17 | 1982-08-10 | Bell Telephone Laboratories, Incorporated | Method of making contact electrodes to silicon gate, and source and drain regions, of a semiconductor device |
USRE32613E (en) * | 1980-04-17 | 1988-02-23 | American Telephone And Telegraph Company, At&T Bell Laboratories | Method of making contact electrodes to silicon gate, and source and drain regions, of a semiconductor device |
IT1131450B (it) * | 1980-05-07 | 1986-06-25 | Cise Spa | Procedimento per la produzione di transistori ad effetto di campo per microonde |
US4320571A (en) * | 1980-10-14 | 1982-03-23 | International Rectifier Corporation | Stencil mask process for high power, high speed controlled rectifiers |
JPS5815250A (ja) * | 1981-07-21 | 1983-01-28 | Fujitsu Ltd | 半導体装置の製造方法 |
US4378628A (en) * | 1981-08-27 | 1983-04-05 | Bell Telephone Laboratories, Incorporated | Cobalt silicide metallization for semiconductor integrated circuits |
US4638347A (en) * | 1982-12-07 | 1987-01-20 | International Business Machines Corporation | Gate electrode sidewall isolation spacer for field effect transistors |
JPS59115189U (ja) * | 1983-01-25 | 1984-08-03 | 三菱重工業株式会社 | 微粉炭管の流量調整オリフイス |
GB2156579B (en) * | 1984-03-15 | 1987-05-07 | Standard Telephones Cables Ltd | Field effect transistors |
JPH0622245B2 (ja) * | 1986-05-02 | 1994-03-23 | 富士ゼロックス株式会社 | 薄膜トランジスタの製造方法 |
JPS6373660A (ja) * | 1986-09-17 | 1988-04-04 | Fujitsu Ltd | 半導体装置 |
US4794093A (en) * | 1987-05-01 | 1988-12-27 | Raytheon Company | Selective backside plating of gaas monolithic microwave integrated circuits |
US4902379A (en) * | 1988-02-08 | 1990-02-20 | Eastman Kodak Company | UHV compatible lift-off method for patterning nobel metal silicide |
JPH05102155A (ja) * | 1991-10-09 | 1993-04-23 | Sony Corp | 銅配線構造体及びその製造方法 |
JP2713165B2 (ja) * | 1994-05-19 | 1998-02-16 | 日本電気株式会社 | 半導体装置の製造方法 |
US8586472B2 (en) * | 2010-07-14 | 2013-11-19 | Infineon Technologies Ag | Conductive lines and pads and method of manufacturing thereof |
US9385005B2 (en) | 2012-12-14 | 2016-07-05 | Fudan University | Semiconductor device and method of making |
WO2014089825A1 (fr) * | 2012-12-14 | 2014-06-19 | 复旦大学 | Dispositif semi-conducteur et son procédé de fabrication |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB1399164A (en) * | 1972-11-08 | 1975-06-25 | Ferranti Ltd | Semiconductor devices |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3382568A (en) * | 1965-07-22 | 1968-05-14 | Ibm | Method for providing electrical connections to semiconductor devices |
US3571913A (en) * | 1968-08-20 | 1971-03-23 | Hewlett Packard Co | Method of making ohmic contact to a shallow diffused transistor |
US3740835A (en) * | 1970-08-31 | 1973-06-26 | Fairchild Camera Instr Co | Method of forming semiconductor device contacts |
JPS4834457A (fr) * | 1971-09-07 | 1973-05-18 | ||
DE2315710C3 (de) * | 1973-03-29 | 1975-11-13 | Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt | Verfahren zum Herstellen einer Halbleiteranordnung |
JPS5321989B2 (fr) * | 1973-10-12 | 1978-07-06 | ||
JPS5847867B2 (ja) * | 1975-02-26 | 1983-10-25 | 日本電気株式会社 | ハンドウタイソウチ |
-
1977
- 1977-05-02 US US05/793,231 patent/US4109372A/en not_active Expired - Lifetime
-
1978
- 1978-03-28 JP JP3495978A patent/JPS53136488A/ja active Granted
- 1978-03-31 FR FR7810335A patent/FR2390003B1/fr not_active Expired
- 1978-04-07 GB GB13699/78A patent/GB1562877A/en not_active Expired
- 1978-04-20 DE DE19782817258 patent/DE2817258A1/de not_active Withdrawn
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB1399164A (en) * | 1972-11-08 | 1975-06-25 | Ferranti Ltd | Semiconductor devices |
Non-Patent Citations (2)
Title |
---|
NV700/73 * |
NV700/74 * |
Also Published As
Publication number | Publication date |
---|---|
DE2817258A1 (de) | 1978-11-09 |
US4109372A (en) | 1978-08-29 |
GB1562877A (en) | 1980-03-19 |
JPS5710585B2 (fr) | 1982-02-26 |
FR2390003B1 (fr) | 1980-08-29 |
JPS53136488A (en) | 1978-11-29 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
ST | Notification of lapse |