GB1399164A - Semiconductor devices - Google Patents

Semiconductor devices

Info

Publication number
GB1399164A
GB1399164A GB5371774A GB5371774A GB1399164A GB 1399164 A GB1399164 A GB 1399164A GB 5371774 A GB5371774 A GB 5371774A GB 5371774 A GB5371774 A GB 5371774A GB 1399164 A GB1399164 A GB 1399164A
Authority
GB
United Kingdom
Prior art keywords
layer
ohmic contact
polycrystalline
silicon
passivating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB5371774A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ferranti International PLC
Original Assignee
Ferranti PLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ferranti PLC filed Critical Ferranti PLC
Priority to GB5371774A priority Critical patent/GB1399164A/en
Priority to US05/543,181 priority patent/US4106051A/en
Publication of GB1399164A publication Critical patent/GB1399164A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53271—Conductive materials containing semiconductor material, e.g. polysilicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

1399164 Semi-conductor devices FERRANTI Ltd 7 Nov 1973 [8 Nov 1972] 53717/74 Divided out of 1399163 Heading H1K A semi-conductor device, e.g. a transistor, having a passivating layer 14 of silicon dioxide on the surface of a monocrystalline silicon body 11 and an ohmic contact extending both to part of the silicon surface exposed through an aperture 16 in the passivating layer 14 and on portions of the passivating layer adjacent the aperture, the ohmic contact comprising a first polycrystalline silicon layer 20, a metal layer 21 of tungsten or molybdenum as the first layer 20 and a second polycrystalline silicon layer 40 on the metal layer 21. The layers of the ohmic contact may be deposited consecutively in the same deposition apparatus as described in the parent Specification 1,399,163. The polycrystalline layers 20, 40 may be doped with a conductivity-type determining impurity, e.g. phosphorus, and may provide a required resistance within the ohmic contact. The ohmic contact may be completed by depositing a gold or aluminium layer 41 on to the second polycrystalline layer 40 such that it forms an intermetallic compound therewith.
GB5371774A 1972-11-08 1972-11-08 Semiconductor devices Expired GB1399164A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
GB5371774A GB1399164A (en) 1972-11-08 1972-11-08 Semiconductor devices
US05/543,181 US4106051A (en) 1972-11-08 1975-01-22 Semiconductor devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB5371774A GB1399164A (en) 1972-11-08 1972-11-08 Semiconductor devices

Publications (1)

Publication Number Publication Date
GB1399164A true GB1399164A (en) 1975-06-25

Family

ID=10468756

Family Applications (1)

Application Number Title Priority Date Filing Date
GB5371774A Expired GB1399164A (en) 1972-11-08 1972-11-08 Semiconductor devices

Country Status (1)

Country Link
GB (1) GB1399164A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2390003A1 (en) * 1977-05-02 1978-12-01 Ibm

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2390003A1 (en) * 1977-05-02 1978-12-01 Ibm

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Legal Events

Date Code Title Description
PS Patent sealed
PCNP Patent ceased through non-payment of renewal fee