FR2366665A1 - Memoire dynamique a circuits integres a semi-conducteurs - Google Patents
Memoire dynamique a circuits integres a semi-conducteursInfo
- Publication number
- FR2366665A1 FR2366665A1 FR7728801A FR7728801A FR2366665A1 FR 2366665 A1 FR2366665 A1 FR 2366665A1 FR 7728801 A FR7728801 A FR 7728801A FR 7728801 A FR7728801 A FR 7728801A FR 2366665 A1 FR2366665 A1 FR 2366665A1
- Authority
- FR
- France
- Prior art keywords
- memory
- dynamic memory
- integrated semiconductor
- semiconductor circuits
- elements
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
- G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
Abstract
L'invention concerne les techniques de calcul. La mémoire dynamique faisant l'objet de l'invention est caractérisée en ce que sa matrice comporte, dans chacune des colonnes 5, un fil numérique supplementaire 7 disposé en parallèle sur le fil numérique 6 et auquel sont reliées l'une des bornes de chaque élément du groupe d'éléments de mémoire 2 et l'une des bornes d'information de l'amplificateur différentiel 10 de la colonne 5, la connexion des éléments de chacun des groupes d'éléments de mémoire 1 et 2 aux fils numériques 6 et 7 correspondants étant réalisée de telle manière que, le long de la colonne 5, au moins un élément de mémoire 1 alterne avec au moins un élément de mémoire 2. L'invention permet notamment d'améliorer la sensibilité des amplificateurs différentiels à la différence de potentiel d'information
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
SU762406945A SU928412A1 (ru) | 1976-09-30 | 1976-09-30 | Матричный накопитель дл интегрального запоминающего устройства |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2366665A1 true FR2366665A1 (fr) | 1978-04-28 |
FR2366665B1 FR2366665B1 (fr) | 1979-09-07 |
Family
ID=20677899
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR7728801A Granted FR2366665A1 (fr) | 1976-09-30 | 1977-09-23 | Memoire dynamique a circuits integres a semi-conducteurs |
Country Status (8)
Country | Link |
---|---|
US (1) | US4133048A (fr) |
JP (1) | JPS5352023A (fr) |
DD (1) | DD132744A1 (fr) |
DE (1) | DE2739276C3 (fr) |
FR (1) | FR2366665A1 (fr) |
GB (1) | GB1552543A (fr) |
NL (1) | NL7709976A (fr) |
SU (1) | SU928412A1 (fr) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2919166C2 (de) * | 1978-05-12 | 1986-01-02 | Nippon Electric Co., Ltd., Tokio/Tokyo | Speichervorrichtung |
JPS58111183A (ja) * | 1981-12-25 | 1983-07-02 | Hitachi Ltd | ダイナミツクram集積回路装置 |
US4494220A (en) * | 1982-11-24 | 1985-01-15 | At&T Bell Laboratories | Folded bit line memory with one decoder per pair of spare rows |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2317729A1 (fr) * | 1975-07-10 | 1977-02-04 | Burroughs Corp | Amplificateur de detection ultrasensible pour memoires a cellules a un seul transistor |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3969706A (en) * | 1974-10-08 | 1976-07-13 | Mostek Corporation | Dynamic random access memory misfet integrated circuit |
-
1976
- 1976-09-30 SU SU762406945A patent/SU928412A1/ru active
-
1977
- 1977-08-31 DE DE2739276A patent/DE2739276C3/de not_active Expired
- 1977-09-12 NL NL7709976A patent/NL7709976A/xx unknown
- 1977-09-12 JP JP10886877A patent/JPS5352023A/ja active Pending
- 1977-09-22 US US05/835,664 patent/US4133048A/en not_active Expired - Lifetime
- 1977-09-23 FR FR7728801A patent/FR2366665A1/fr active Granted
- 1977-09-28 DD DD7700201249A patent/DD132744A1/xx unknown
- 1977-09-30 GB GB40808/77A patent/GB1552543A/en not_active Expired
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2317729A1 (fr) * | 1975-07-10 | 1977-02-04 | Burroughs Corp | Amplificateur de detection ultrasensible pour memoires a cellules a un seul transistor |
Also Published As
Publication number | Publication date |
---|---|
NL7709976A (nl) | 1978-04-03 |
SU928412A1 (ru) | 1982-05-15 |
DE2739276B2 (de) | 1979-10-11 |
FR2366665B1 (fr) | 1979-09-07 |
DD132744A1 (de) | 1978-10-25 |
DE2739276A1 (de) | 1978-04-06 |
JPS5352023A (en) | 1978-05-12 |
GB1552543A (en) | 1979-09-12 |
US4133048A (en) | 1979-01-02 |
DE2739276C3 (de) | 1981-03-12 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
ST | Notification of lapse |