FR2340620A1 - Procede de fabrication d'un dispositif integre a grande echelle ayant une surface plane - Google Patents

Procede de fabrication d'un dispositif integre a grande echelle ayant une surface plane

Info

Publication number
FR2340620A1
FR2340620A1 FR7639828A FR7639828A FR2340620A1 FR 2340620 A1 FR2340620 A1 FR 2340620A1 FR 7639828 A FR7639828 A FR 7639828A FR 7639828 A FR7639828 A FR 7639828A FR 2340620 A1 FR2340620 A1 FR 2340620A1
Authority
FR
France
Prior art keywords
manufacturing process
flat surface
integrated device
scale integrated
scale
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7639828A
Other languages
English (en)
French (fr)
Other versions
FR2340620B1 (de
Inventor
Ekkehard F Miersch
Hwa N Yu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of FR2340620A1 publication Critical patent/FR2340620A1/fr
Application granted granted Critical
Publication of FR2340620B1 publication Critical patent/FR2340620B1/fr
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/7688—Filling of holes, grooves or trenches, e.g. vias, with conductive material by deposition over sacrificial masking layer, e.g. lift-off

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Weting (AREA)
FR7639828A 1976-02-06 1976-12-30 Procede de fabrication d'un dispositif integre a grande echelle ayant une surface plane Granted FR2340620A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US65581476A 1976-02-06 1976-02-06

Publications (2)

Publication Number Publication Date
FR2340620A1 true FR2340620A1 (fr) 1977-09-02
FR2340620B1 FR2340620B1 (de) 1979-09-28

Family

ID=24630480

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7639828A Granted FR2340620A1 (fr) 1976-02-06 1976-12-30 Procede de fabrication d'un dispositif integre a grande echelle ayant une surface plane

Country Status (6)

Country Link
JP (1) JPS5827664B2 (de)
CA (1) CA1088382A (de)
DE (1) DE2703473A1 (de)
FR (1) FR2340620A1 (de)
GB (1) GB1521431A (de)
IT (1) IT1079545B (de)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0008359A2 (de) * 1978-08-21 1980-03-05 International Business Machines Corporation Verfahren zum Herstellen einer Dünnfilmstruktur

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59170692A (ja) * 1983-03-16 1984-09-26 Ebara Corp 水封入熱交換器
WO2017071702A1 (de) 2015-10-27 2017-05-04 Schaeffler Technologies AG & Co. KG Lageranordnung mit darin eingebauter elektrischer leitung zur bereitstellung von mehreren betriebsspannungen

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1267738B (de) * 1962-10-29 1968-05-09 Intellux Inc Verfahren zur Herstellung von elektrischen Verbindungen zwischen den Stromkreisen von mehrlagigen gedruckten elektrischen Schaltungen
US3464855A (en) * 1966-09-06 1969-09-02 North American Rockwell Process for forming interconnections in a multilayer circuit board
DE1765013A1 (de) * 1968-03-21 1971-07-01 Telefunken Patent Verfahren zur Herstellung von Mehrebenenschaltungen
DE2059425A1 (de) * 1970-12-02 1972-06-22 Siemens Ag Partieller Aufbau von gedruckten Mehrlagenschaltungen
JPS4960870A (de) * 1972-10-16 1974-06-13
US3873361A (en) * 1973-11-29 1975-03-25 Ibm Method of depositing thin film utilizing a lift-off mask
JPS5120681A (en) * 1974-07-27 1976-02-19 Oki Electric Ind Co Ltd Handotaisochino seizohoho
NL7415841A (nl) * 1974-12-05 1976-06-09 Philips Nv Werkwijze voor het vervaardigen van een half- geleiderinrichting en halfgeleiderinrichting, vervaardigd volgens de werkwijze.
JPS5272571A (en) * 1975-12-15 1977-06-17 Fujitsu Ltd Production of semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0008359A2 (de) * 1978-08-21 1980-03-05 International Business Machines Corporation Verfahren zum Herstellen einer Dünnfilmstruktur
EP0008359A3 (en) * 1978-08-21 1980-03-19 International Business Machines Corporation Process for making a thin-film structure

Also Published As

Publication number Publication date
FR2340620B1 (de) 1979-09-28
GB1521431A (en) 1978-08-16
CA1088382A (en) 1980-10-28
IT1079545B (it) 1985-05-13
JPS5827664B2 (ja) 1983-06-10
DE2703473C2 (de) 1991-01-24
DE2703473A1 (de) 1977-08-11
JPS5295987A (en) 1977-08-12

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Legal Events

Date Code Title Description
ST Notification of lapse