ES8603095A1 - Una disposicion de arquitectura de linea general interna para una instalacion de calculo electronico digital de alta velocidad - Google Patents

Una disposicion de arquitectura de linea general interna para una instalacion de calculo electronico digital de alta velocidad

Info

Publication number
ES8603095A1
ES8603095A1 ES536181A ES536181A ES8603095A1 ES 8603095 A1 ES8603095 A1 ES 8603095A1 ES 536181 A ES536181 A ES 536181A ES 536181 A ES536181 A ES 536181A ES 8603095 A1 ES8603095 A1 ES 8603095A1
Authority
ES
Spain
Prior art keywords
bus
cpu
unit
data
internal bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
ES536181A
Other languages
English (en)
Other versions
ES536181A0 (es
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of ES8603095A1 publication Critical patent/ES8603095A1/es
Publication of ES536181A0 publication Critical patent/ES536181A0/es
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G06F9/30043—LOAD or STORE instructions; Clear instruction
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F02—COMBUSTION ENGINES; HOT-GAS OR COMBUSTION-PRODUCT ENGINE PLANTS
    • F02B—INTERNAL-COMBUSTION PISTON ENGINES; COMBUSTION ENGINES IN GENERAL
    • F02B75/00—Other engines
    • F02B75/02—Engines characterised by their cycles, e.g. six-stroke
    • F02B2075/022—Engines characterised by their cycles, e.g. six-stroke having less than six strokes per cycle
    • F02B2075/027—Engines characterised by their cycles, e.g. six-stroke having less than six strokes per cycle four

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
  • Bus Control (AREA)

Abstract

ARQUITECTURA DE LINEA GENERAL INTERNA PARA PROCESADOR. LA ARQUITECTURA DEL MECANISMO DE LINEA GENERAL INTERNA DEFINE UN FORMATO DE INSTRUCCIONES DE LINEA GENERAL QUE ESPECIFICA LA UNIDAD DE LINEA GENERAL QUE SE ESTA SOLICITANDO, Y DATOS SUFICIENTES PARA ESPECIFICAR LOS OPERANDOS NECESARIOS PARA REALIZAR LAS INSTRUCCIONES SOLICITADAS. SE CREAN DOS CLASES BASICAS DE INSTRUCCIONES, UNA EN LA QUE EL PROCESADOR CENTRAL ESPERA HASTA QUE SE REALIZA UNA OPERACION SOLICITADA, Y OTRA EN LA CUAL DICHO PROCESADOR EMITE UNA INSTRUCCION PARA UNA UNIDAD DE LINEA GENERAL Y CONTINUA EJECUTANDO INSTRUCCIONES ADICIONALES EN PARALELO CON LA OPERACION DE LA UNIDAD DE LINEA GENERAL.
ES536181A 1983-12-29 1984-09-24 Una disposicion de arquitectura de linea general interna para una instalacion de calculo electronico digital de alta velocidad Granted ES536181A0 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/566,925 US4947316A (en) 1983-12-29 1983-12-29 Internal bus architecture employing a simplified rapidly executable instruction set

Publications (2)

Publication Number Publication Date
ES8603095A1 true ES8603095A1 (es) 1985-10-16
ES536181A0 ES536181A0 (es) 1985-10-16

Family

ID=24264994

Family Applications (1)

Application Number Title Priority Date Filing Date
ES536181A Granted ES536181A0 (es) 1983-12-29 1984-09-24 Una disposicion de arquitectura de linea general interna para una instalacion de calculo electronico digital de alta velocidad

Country Status (8)

Country Link
US (1) US4947316A (es)
EP (1) EP0148975B1 (es)
JP (1) JPS60142743A (es)
AU (1) AU574737B2 (es)
BR (1) BR8406533A (es)
CA (1) CA1217869A (es)
DE (1) DE3483152D1 (es)
ES (1) ES536181A0 (es)

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JPS63259727A (ja) * 1987-04-17 1988-10-26 Hitachi Ltd コプロセツサのインタ−フエイス方式
JPH02190930A (ja) * 1988-12-29 1990-07-26 Internatl Business Mach Corp <Ibm> ソフトウエア命令実行装置
JPH02188866A (ja) * 1989-01-17 1990-07-24 Fujitsu Ltd コプロセッサにおける事象管理方式
JPH0314025A (ja) * 1989-06-13 1991-01-22 Nec Corp 命令実行制御方式
DE69130233T2 (de) * 1990-03-15 1999-05-20 Sun Microsystems Inc Verfahren und gerät um ein sperrungscache einzusetzen
US5418956A (en) * 1992-02-26 1995-05-23 Microsoft Corporation Method and system for avoiding selector loads
US5535405A (en) * 1993-12-23 1996-07-09 Unisys Corporation Microsequencer bus controller system
US6151661A (en) * 1994-03-03 2000-11-21 International Business Machines Corporation Cache memory storage space management system and method
US5787472A (en) * 1995-07-31 1998-07-28 Ibm Corporation Disk caching system for selectively providing interval caching or segment caching of vided data
JP2933027B2 (ja) * 1996-08-30 1999-08-09 日本電気株式会社 複数命令並列発行／実行管理装置
KR100417398B1 (ko) * 1996-09-11 2004-04-03 엘지전자 주식회사 디에스피의명령어블록반복처리방법
US6256693B1 (en) * 1999-07-15 2001-07-03 3Com Corporation Master/slave data bus employing undirectional address and data lines and request/acknowledge signaling
US6658510B1 (en) * 2000-10-18 2003-12-02 International Business Machines Corporation Software method to retry access to peripherals that can cause bus timeouts during momentary busy periods
US20060136608A1 (en) * 2004-12-22 2006-06-22 Gilbert Jeffrey D System and method for control registers accessed via private operations
US9405534B2 (en) 2013-01-21 2016-08-02 Tom Yap Compound complex instruction set computer (CCISC) processor architecture
US9110657B2 (en) 2013-01-21 2015-08-18 Tom Yap Flowchart compiler for a compound complex instruction set computer (CCISC) processor architecture
GB201709752D0 (en) * 2017-06-19 2017-08-02 Advanced Risc Mach Ltd Graphics processing systems
CN113366438A (zh) 2019-01-31 2021-09-07 国际商业机器公司 处理输入/输出存储指令
TWI773959B (zh) 2019-01-31 2022-08-11 美商萬國商業機器公司 用於處理輸入輸出儲存指令之資料處理系統、方法及電腦程式產品
TWI767175B (zh) 2019-01-31 2022-06-11 美商萬國商業機器公司 用於處理輸入輸出儲存指令之資料處理系統、方法及電腦程式產品
DE112020000146T5 (de) 2019-01-31 2021-09-09 International Business Machines Corporation Handhabung einer eingabe-/ausgabe-speicheranweisung

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Publication number Priority date Publication date Assignee Title
US3753234A (en) * 1972-02-25 1973-08-14 Reliance Electric Co Multicomputer system with simultaneous data interchange between computers
CA1013861A (en) * 1972-10-10 1977-07-12 Adrianus J. Van De Goor Special instruction processor
US4014006A (en) * 1973-08-10 1977-03-22 Data General Corporation Data processing system having a unique cpu and memory tuning relationship and data path configuration
US4128876A (en) * 1977-04-28 1978-12-05 International Business Machines Corporation Synchronous microcode generated interface for system of microcoded data processors
US4270167A (en) * 1978-06-30 1981-05-26 Intel Corporation Apparatus and method for cooperative and concurrent coprocessing of digital information
JPS602705B2 (ja) * 1978-11-06 1985-01-23 株式会社東芝 オプシヨン接続方式
JPS55150041A (en) * 1979-05-11 1980-11-21 Hitachi Ltd Arithmetic processor
US4338675A (en) * 1980-02-13 1982-07-06 Intel Corporation Numeric data processor
US4493020A (en) * 1980-05-06 1985-01-08 Burroughs Corporation Microprogrammed digital data processor employing microinstruction tasking and dynamic register allocation
JPS57164340A (en) * 1981-04-03 1982-10-08 Hitachi Ltd Information processing method
US4467412A (en) * 1981-05-18 1984-08-21 Atari, Inc. Slave processor with clock controlled by internal ROM & master processor
US4530051A (en) * 1982-09-10 1985-07-16 At&T Bell Laboratories Program process execution in a distributed multiprocessor system
US4594660A (en) * 1982-10-13 1986-06-10 Honeywell Information Systems Inc. Collector
US4638453A (en) * 1983-03-28 1987-01-20 Motorola, Inc. Signal processing unit
US4564901A (en) * 1983-07-21 1986-01-14 Burroughs Corporation Method of performing a sequence of related activities via multiple asynchronously intercoupled digital processors

Also Published As

Publication number Publication date
BR8406533A (pt) 1985-10-15
AU3548884A (en) 1985-07-04
AU574737B2 (en) 1988-07-14
EP0148975A2 (en) 1985-07-24
CA1217869A (en) 1987-02-10
EP0148975B1 (en) 1990-09-05
JPH0135367B2 (es) 1989-07-25
DE3483152D1 (de) 1990-10-11
US4947316A (en) 1990-08-07
ES536181A0 (es) 1985-10-16
EP0148975A3 (en) 1988-02-03
JPS60142743A (ja) 1985-07-27

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Legal Events

Date Code Title Description
FD1A Patent lapsed

Effective date: 19980302