JPS6482164A - Communication system - Google Patents

Communication system

Info

Publication number
JPS6482164A
JPS6482164A JP24012987A JP24012987A JPS6482164A JP S6482164 A JPS6482164 A JP S6482164A JP 24012987 A JP24012987 A JP 24012987A JP 24012987 A JP24012987 A JP 24012987A JP S6482164 A JPS6482164 A JP S6482164A
Authority
JP
Japan
Prior art keywords
cpu
data
communication
constitution
hard disk
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP24012987A
Other languages
Japanese (ja)
Inventor
Tatsuo Okano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP24012987A priority Critical patent/JPS6482164A/en
Publication of JPS6482164A publication Critical patent/JPS6482164A/en
Pending legal-status Critical Current

Links

Landscapes

  • Multi Processors (AREA)

Abstract

PURPOSE:To omit a memory error for inter-CPU communication just with the addition of a simple circuit by securing such a constitution where a CPU transfers the reception data to a hard disk via a hard disk controller to store it there and then sends the reception data to a window memory to decode it. CONSTITUTION:A means 6 is used to decode the address data received from a microprocessor 1 and a hard disk 14 can receive an access from a bus set between microprocessors CPU 1. When the communication is carried out between both CPUs 1, the CPU 1 of the transmission side writes data into the disk 14 of the CPU 1 of the reception side. When this data writing job is through, the CPU 1 of the reception side processes the data on the disk 14. In such a way, the system constitution is simplified and the communication is performed without using a buffer memory.
JP24012987A 1987-09-24 1987-09-24 Communication system Pending JPS6482164A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24012987A JPS6482164A (en) 1987-09-24 1987-09-24 Communication system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24012987A JPS6482164A (en) 1987-09-24 1987-09-24 Communication system

Publications (1)

Publication Number Publication Date
JPS6482164A true JPS6482164A (en) 1989-03-28

Family

ID=17054929

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24012987A Pending JPS6482164A (en) 1987-09-24 1987-09-24 Communication system

Country Status (1)

Country Link
JP (1) JPS6482164A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009119886A1 (en) * 2008-03-26 2009-10-01 セイコーエプソン株式会社 Liquid storing body

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009119886A1 (en) * 2008-03-26 2009-10-01 セイコーエプソン株式会社 Liquid storing body
JP2009255550A (en) * 2008-03-26 2009-11-05 Seiko Epson Corp Liquid storing body
CN102741053A (en) * 2008-03-26 2012-10-17 精工爱普生株式会社 Liquid storing body
US8335978B2 (en) 2008-03-26 2012-12-18 Seiko Epson Corporation Liquid container

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