ES2144488T3 - Sistema de tratamiento de datos que emplea coherencia de antememoria empleando un protocolo de escrutinio. - Google Patents

Sistema de tratamiento de datos que emplea coherencia de antememoria empleando un protocolo de escrutinio.

Info

Publication number
ES2144488T3
ES2144488T3 ES94306613T ES94306613T ES2144488T3 ES 2144488 T3 ES2144488 T3 ES 2144488T3 ES 94306613 T ES94306613 T ES 94306613T ES 94306613 T ES94306613 T ES 94306613T ES 2144488 T3 ES2144488 T3 ES 2144488T3
Authority
ES
Spain
Prior art keywords
sector
snoop
page
granularity
data processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES94306613T
Other languages
English (en)
Inventor
Ravi Kumar Arimilli
Dennis Gerard Gregoire
Amy May Youngs
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of ES2144488T3 publication Critical patent/ES2144488T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
    • G06F12/0835—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means for main memory peripheral accesses (e.g. I/O or DMA)

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Storage Device Security (AREA)

Abstract

UN SISTEMA Y UN METODO DE PROCESAMIENTO DE DATOS CAMBIA DINAMICAMENTE LA GRANULARIDAD DE COMPARACION DE UN CIRCUITO ENTRE UN SECTOR Y UNA PAGINA, DEPENDIENDO DEL ESTADO (ACTIVO O INACTIVO) DE UN DISPOSITIVO I/O DE ACCESO DE MEMORIA DIRECTO (DMA) 20,22 QUE ESTA ESCRIBIENDO A UN DISPOSITIVO 7 SOBRE EL BUS DEL SISTEMA 5 ASINCRONICAMENTE CUANDO SE COMPARA CON EL RELOJ DE LA CPU 1. USANDO GRANULARIDAD DE DIRECCION DE PAGINA, NO ACONTECERAN ACIERTOS DE CIRCUITO ERRONEOS, YA QUE LAS DIRECCIONES DE SECTORES POTENCIALMENTE INVALIDOS NO SE USAN DURANTE LA COMPARACION DE CIRCUITO. LAS DIRECCIONES DE MEMORIA DE SECTOR PUEDEN ESTAR EN UN ESTADO DE TRANSICION EN EL MOMENTO QUE EL RELOJ DE LA CPU DETERMINA QUE TENGA LUGAR UNA COMPARACION DE CIRCUITO, PORQUE ESTA DIRECCION DE SECTOR HA SIDO REQUERIDA POR UN DISPOSITIVO QUE OPERE ASINCRONICAMENTE CON EL RELOJ DE LA CPU. UNA VEZ EL DISPOSITIVO ASINCRONICO SE VUELVE INACTIVO, EL SISTEMA RETORNA DINAMICAMENTE UNA GRANULARIDAD DE COMPARACION DE CIRCUITO DE DIRECCION DE SECTOR Y PAGINA.
ES94306613T 1993-09-20 1994-09-08 Sistema de tratamiento de datos que emplea coherencia de antememoria empleando un protocolo de escrutinio. Expired - Lifetime ES2144488T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/123,820 US5526512A (en) 1993-09-20 1993-09-20 Dynamic management of snoop granularity for a coherent asynchronous DMA cache

Publications (1)

Publication Number Publication Date
ES2144488T3 true ES2144488T3 (es) 2000-06-16

Family

ID=22411087

Family Applications (1)

Application Number Title Priority Date Filing Date
ES94306613T Expired - Lifetime ES2144488T3 (es) 1993-09-20 1994-09-08 Sistema de tratamiento de datos que emplea coherencia de antememoria empleando un protocolo de escrutinio.

Country Status (8)

Country Link
US (1) US5526512A (es)
EP (1) EP0644491B1 (es)
JP (1) JP2642064B2 (es)
KR (1) KR970007271B1 (es)
AT (1) ATE191803T1 (es)
CA (1) CA2125218A1 (es)
DE (1) DE69423938T2 (es)
ES (1) ES2144488T3 (es)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5781763A (en) * 1995-04-07 1998-07-14 International Business Machines Corporation Independent control of DMA and I/O resources for mixed-endian computing systems
US6128711A (en) * 1996-11-12 2000-10-03 Compaq Computer Corporation Performance optimization and system bus duty cycle reduction by I/O bridge partial cache line writes
US5809528A (en) * 1996-12-24 1998-09-15 International Business Machines Corporation Method and circuit for a least recently used replacement mechanism and invalidated address handling in a fully associative many-way cache memory
US5958011A (en) * 1997-03-31 1999-09-28 International Business Machines Corporation System utilizing mastering and snooping circuitry that operate in response to clock signals having different frequencies generated by the communication controller
US5937167A (en) * 1997-03-31 1999-08-10 International Business Machines Corporation Communication controller for generating four timing signals each of selectable frequency for transferring data across a network
US6173371B1 (en) * 1997-04-14 2001-01-09 International Business Machines Corporation Demand-based issuance of cache operations to a processor bus
KR100455116B1 (ko) * 1997-10-23 2004-12-30 엘지전자 주식회사 내장시스템의메모리액세스방법
US6792424B1 (en) 1999-04-23 2004-09-14 International Business Machines Corporation System and method for managing authentication and coherency in a storage area network
US7062612B2 (en) * 2002-12-12 2006-06-13 International Business Machines Corporation Updating remote locked cache
FR2864730B1 (fr) * 2003-12-26 2006-03-17 Temento Systems Dispositif de memorisation
US7395448B2 (en) * 2006-07-26 2008-07-01 International Business Machines Corporation Directly obtaining by application programs information usable in determining clock accuracy
US10248567B2 (en) 2014-06-16 2019-04-02 Hewlett-Packard Development Company, L.P. Cache coherency for direct memory access operations

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3638947C2 (de) * 1986-11-14 1995-08-31 Bosch Gmbh Robert Verfahren zur Synchronisation von Rechnern eines Mehrrechnersystems und Mehrrechnersystem
JPH01118944A (ja) * 1987-10-31 1989-05-11 Toshiba Corp キャッシュメモリ制御装置
US4928225A (en) * 1988-08-25 1990-05-22 Edgcore Technology, Inc. Coherent cache structures and methods
JPH0778765B2 (ja) * 1988-09-08 1995-08-23 富士通株式会社 キャッシュ内蔵プロセッサ
US5025365A (en) * 1988-11-14 1991-06-18 Unisys Corporation Hardware implemented cache coherency protocol with duplicated distributed directories for high-performance multiprocessors
EP0377970B1 (en) * 1989-01-13 1995-08-16 International Business Machines Corporation I/O caching
US5287482A (en) * 1989-01-13 1994-02-15 International Business Machines Corporation Input/output cache
US5133074A (en) * 1989-02-08 1992-07-21 Acer Incorporated Deadlock resolution with cache snooping
JPH0630094B2 (ja) * 1989-03-13 1994-04-20 インターナショナル・ビジネス・マシーンズ・コーポレイション マルチプロセツサ・システム
US5072369A (en) * 1989-04-07 1991-12-10 Tektronix, Inc. Interface between buses attached with cached modules providing address space mapped cache coherent memory access with SNOOP hit memory updates
US5119485A (en) * 1989-05-15 1992-06-02 Motorola, Inc. Method for data bus snooping in a data processing system by selective concurrent read and invalidate cache operation
JPH0348951A (ja) * 1989-07-18 1991-03-01 Fujitsu Ltd アドレスモニタ装置
JPH03219345A (ja) * 1990-01-25 1991-09-26 Toshiba Corp 多ポートキャッシュメモリ制御装置
US5263142A (en) * 1990-04-12 1993-11-16 Sun Microsystems, Inc. Input/output cache with mapped pages allocated for caching direct (virtual) memory access input/output data based on type of I/O devices
US5202973A (en) * 1990-06-29 1993-04-13 Digital Equipment Corporation Method of controlling a shared memory bus in a multiprocessor system for preventing bus collisions and for ensuring a full bus
US5193170A (en) * 1990-10-26 1993-03-09 International Business Machines Corporation Methods and apparatus for maintaining cache integrity whenever a cpu write to rom operation is performed with rom mapped to ram
JPH04132550U (ja) * 1991-05-23 1992-12-08 横河電機株式会社 マルチプロセツサシステム
US5228134A (en) * 1991-06-04 1993-07-13 Intel Corporation Cache memory integrated circuit for use with a synchronous central processor bus and an asynchronous memory bus
US5293603A (en) * 1991-06-04 1994-03-08 Intel Corporation Cache subsystem for microprocessor based computer system with synchronous and asynchronous data path
GB2256512B (en) * 1991-06-04 1995-03-15 Intel Corp Second level cache controller unit and system
GB2272315B (en) * 1991-07-02 1995-10-04 Intel Corp Asynchronous modular bus architecture with burst capability
JPH05189359A (ja) * 1992-01-16 1993-07-30 Hitachi Ltd キャッシュメモリ制御方式
US5325503A (en) * 1992-02-21 1994-06-28 Compaq Computer Corporation Cache memory system which snoops an operation to a first location in a cache line and does not snoop further operations to locations in the same line
EP0559409B1 (en) * 1992-03-04 1998-07-22 Motorola, Inc. A method and apparatus for performing a bus arbitration protocol in a data processing system
US5398325A (en) * 1992-05-07 1995-03-14 Sun Microsystems, Inc. Methods and apparatus for improving cache consistency using a single copy of a cache tag memory in multiple processor computer systems

Also Published As

Publication number Publication date
JPH07105090A (ja) 1995-04-21
ATE191803T1 (de) 2000-04-15
DE69423938D1 (de) 2000-05-18
EP0644491A1 (en) 1995-03-22
US5526512A (en) 1996-06-11
KR970007271B1 (ko) 1997-05-07
EP0644491B1 (en) 2000-04-12
CA2125218A1 (en) 1995-03-21
KR950009444A (ko) 1995-04-24
JP2642064B2 (ja) 1997-08-20
DE69423938T2 (de) 2000-10-12

Similar Documents

Publication Publication Date Title
US6651115B2 (en) DMA controller and coherency-tracking unit for efficient data transfers between coherent and non-coherent memory spaces
KR920000040A (ko) 카피-백 데이타 캐시를 구비한 데이타 치리기
SE9101325D0 (sv) Foerfarande foer att oeka databehandlingshastigheten i datasystem
KR890017609A (ko) 멀티프로세서 데이타 처리시스템 및 그것에 사용되는 캐시장치
EP0301354A3 (en) Cache consistency protocol for multiprocessor system
ES2144488T3 (es) Sistema de tratamiento de datos que emplea coherencia de antememoria empleando un protocolo de escrutinio.
KR970076247A (ko) 데이타 처리 시스템내의 레지스터 액세스 방법 및 장치
EP0285346A3 (en) Cache memory device
US5890216A (en) Apparatus and method for decreasing the access time to non-cacheable address space in a computer system
EP0833341A3 (en) Circuit for controlling writing data to memory
EP0732656A3 (en) Cache MMU system
DK462888A (da) Dataoverfoeringskredsloeb
JPS559228A (en) Memory request control system
JPS5577072A (en) Buffer memory control system
KR970071241A (ko) 다중처리 시스템의 캐시 스테이트 램(ram) 관리방법
JPS57200985A (en) Buffer memory device
KR940009853A (ko) 주행정 전산망시스템(ticom)의 캐시응집을 위한 버스동작 제어방법
KR970049517A (ko) 고속 중형컴퓨터에 있어서 isdn보드의 데이타 전달방법
KR940004446A (ko) 버스 인터페이스 장치
RU95120615A (ru) Устройство расширения памяти для вычислительных устройств и систем
KR910012928A (ko) 컴퓨터의 메모리 확장 시스템
JPH07105086A (ja) バススヌープ制御装置
KR930014034A (ko) 캐쉬 코히어런시 프로토콜 방법 및 장치
KR960001990A (ko) 프로세서의 내부데이타 캐쉬 무효화 수행회로
KR910006845A (ko) 중앙처리장치의 메모리 확장장치

Legal Events

Date Code Title Description
FG2A Definitive protection

Ref document number: 644491

Country of ref document: ES