DE69423938D1 - Datenverarbeitungssystem mit Aufrechterhaltung der Cachespeicherkohärenz unter Verwendung eines Snoopprotokolls - Google Patents

Datenverarbeitungssystem mit Aufrechterhaltung der Cachespeicherkohärenz unter Verwendung eines Snoopprotokolls

Info

Publication number
DE69423938D1
DE69423938D1 DE69423938T DE69423938T DE69423938D1 DE 69423938 D1 DE69423938 D1 DE 69423938D1 DE 69423938 T DE69423938 T DE 69423938T DE 69423938 T DE69423938 T DE 69423938T DE 69423938 D1 DE69423938 D1 DE 69423938D1
Authority
DE
Germany
Prior art keywords
snoop
sector
data processing
page
processing system
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69423938T
Other languages
English (en)
Other versions
DE69423938T2 (de
Inventor
Ravi Kumar Arimilli
Dennis Gerard Gregoire
Amy May Youngs
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE69423938D1 publication Critical patent/DE69423938D1/de
Publication of DE69423938T2 publication Critical patent/DE69423938T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
    • G06F12/0835—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means for main memory peripheral accesses (e.g. I/O or DMA)

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Storage Device Security (AREA)
DE69423938T 1993-09-20 1994-09-08 Datenverarbeitungssystem mit Aufrechterhaltung der Cachespeicherkohärenz unter Verwendung eines Snoopprotokolls Expired - Fee Related DE69423938T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/123,820 US5526512A (en) 1993-09-20 1993-09-20 Dynamic management of snoop granularity for a coherent asynchronous DMA cache

Publications (2)

Publication Number Publication Date
DE69423938D1 true DE69423938D1 (de) 2000-05-18
DE69423938T2 DE69423938T2 (de) 2000-10-12

Family

ID=22411087

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69423938T Expired - Fee Related DE69423938T2 (de) 1993-09-20 1994-09-08 Datenverarbeitungssystem mit Aufrechterhaltung der Cachespeicherkohärenz unter Verwendung eines Snoopprotokolls

Country Status (8)

Country Link
US (1) US5526512A (de)
EP (1) EP0644491B1 (de)
JP (1) JP2642064B2 (de)
KR (1) KR970007271B1 (de)
AT (1) ATE191803T1 (de)
CA (1) CA2125218A1 (de)
DE (1) DE69423938T2 (de)
ES (1) ES2144488T3 (de)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5781763A (en) * 1995-04-07 1998-07-14 International Business Machines Corporation Independent control of DMA and I/O resources for mixed-endian computing systems
US6128711A (en) * 1996-11-12 2000-10-03 Compaq Computer Corporation Performance optimization and system bus duty cycle reduction by I/O bridge partial cache line writes
US5809528A (en) * 1996-12-24 1998-09-15 International Business Machines Corporation Method and circuit for a least recently used replacement mechanism and invalidated address handling in a fully associative many-way cache memory
US5937167A (en) * 1997-03-31 1999-08-10 International Business Machines Corporation Communication controller for generating four timing signals each of selectable frequency for transferring data across a network
US5958011A (en) * 1997-03-31 1999-09-28 International Business Machines Corporation System utilizing mastering and snooping circuitry that operate in response to clock signals having different frequencies generated by the communication controller
US6173371B1 (en) * 1997-04-14 2001-01-09 International Business Machines Corporation Demand-based issuance of cache operations to a processor bus
KR100455116B1 (ko) * 1997-10-23 2004-12-30 엘지전자 주식회사 내장시스템의메모리액세스방법
US6792424B1 (en) 1999-04-23 2004-09-14 International Business Machines Corporation System and method for managing authentication and coherency in a storage area network
US7062612B2 (en) * 2002-12-12 2006-06-13 International Business Machines Corporation Updating remote locked cache
FR2864730B1 (fr) * 2003-12-26 2006-03-17 Temento Systems Dispositif de memorisation
US7395448B2 (en) * 2006-07-26 2008-07-01 International Business Machines Corporation Directly obtaining by application programs information usable in determining clock accuracy
US10248567B2 (en) 2014-06-16 2019-04-02 Hewlett-Packard Development Company, L.P. Cache coherency for direct memory access operations

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3638947C2 (de) * 1986-11-14 1995-08-31 Bosch Gmbh Robert Verfahren zur Synchronisation von Rechnern eines Mehrrechnersystems und Mehrrechnersystem
JPH01118944A (ja) * 1987-10-31 1989-05-11 Toshiba Corp キャッシュメモリ制御装置
US4928225A (en) * 1988-08-25 1990-05-22 Edgcore Technology, Inc. Coherent cache structures and methods
JPH0778765B2 (ja) * 1988-09-08 1995-08-23 富士通株式会社 キャッシュ内蔵プロセッサ
US5025365A (en) * 1988-11-14 1991-06-18 Unisys Corporation Hardware implemented cache coherency protocol with duplicated distributed directories for high-performance multiprocessors
DE68923863T2 (de) * 1989-01-13 1996-03-28 Ibm Ein-/Ausgabecachespeicherung.
US5287482A (en) * 1989-01-13 1994-02-15 International Business Machines Corporation Input/output cache
US5133074A (en) * 1989-02-08 1992-07-21 Acer Incorporated Deadlock resolution with cache snooping
JPH0630094B2 (ja) * 1989-03-13 1994-04-20 インターナショナル・ビジネス・マシーンズ・コーポレイション マルチプロセツサ・システム
US5072369A (en) * 1989-04-07 1991-12-10 Tektronix, Inc. Interface between buses attached with cached modules providing address space mapped cache coherent memory access with SNOOP hit memory updates
US5119485A (en) * 1989-05-15 1992-06-02 Motorola, Inc. Method for data bus snooping in a data processing system by selective concurrent read and invalidate cache operation
JPH0348951A (ja) * 1989-07-18 1991-03-01 Fujitsu Ltd アドレスモニタ装置
JPH03219345A (ja) * 1990-01-25 1991-09-26 Toshiba Corp 多ポートキャッシュメモリ制御装置
US5263142A (en) * 1990-04-12 1993-11-16 Sun Microsystems, Inc. Input/output cache with mapped pages allocated for caching direct (virtual) memory access input/output data based on type of I/O devices
US5202973A (en) * 1990-06-29 1993-04-13 Digital Equipment Corporation Method of controlling a shared memory bus in a multiprocessor system for preventing bus collisions and for ensuring a full bus
US5193170A (en) * 1990-10-26 1993-03-09 International Business Machines Corporation Methods and apparatus for maintaining cache integrity whenever a cpu write to rom operation is performed with rom mapped to ram
JPH04132550U (ja) * 1991-05-23 1992-12-08 横河電機株式会社 マルチプロセツサシステム
US5293603A (en) * 1991-06-04 1994-03-08 Intel Corporation Cache subsystem for microprocessor based computer system with synchronous and asynchronous data path
US5228134A (en) * 1991-06-04 1993-07-13 Intel Corporation Cache memory integrated circuit for use with a synchronous central processor bus and an asynchronous memory bus
GB2256512B (en) * 1991-06-04 1995-03-15 Intel Corp Second level cache controller unit and system
DE4292241C2 (de) * 1991-07-02 1998-04-16 Intel Corp Einrichtung und Verfahren zum sequentiellen Durchführen mehrerer Bustransaktionen zwischen einem Prozessor und vorinstallierten Speichermodulen in einem Computersystem
JPH05189359A (ja) * 1992-01-16 1993-07-30 Hitachi Ltd キャッシュメモリ制御方式
US5325503A (en) * 1992-02-21 1994-06-28 Compaq Computer Corporation Cache memory system which snoops an operation to a first location in a cache line and does not snoop further operations to locations in the same line
DE69319763T2 (de) * 1992-03-04 1999-03-11 Motorola, Inc., Schaumburg, Ill. Verfahren und Gerät zur Durchführung eines Busarbitrierungsprotokolls in einem Datenverarbeitungssystem
US5398325A (en) * 1992-05-07 1995-03-14 Sun Microsystems, Inc. Methods and apparatus for improving cache consistency using a single copy of a cache tag memory in multiple processor computer systems

Also Published As

Publication number Publication date
EP0644491A1 (de) 1995-03-22
EP0644491B1 (de) 2000-04-12
KR970007271B1 (ko) 1997-05-07
DE69423938T2 (de) 2000-10-12
JPH07105090A (ja) 1995-04-21
CA2125218A1 (en) 1995-03-21
US5526512A (en) 1996-06-11
KR950009444A (ko) 1995-04-24
JP2642064B2 (ja) 1997-08-20
ATE191803T1 (de) 2000-04-15
ES2144488T3 (es) 2000-06-16

Similar Documents

Publication Publication Date Title
US6651115B2 (en) DMA controller and coherency-tracking unit for efficient data transfers between coherent and non-coherent memory spaces
US4959777A (en) Write-shared cache circuit for multiprocessor system
US5561779A (en) Processor board having a second level writeback cache system and a third level writethrough cache system which stores exclusive state information for use in a multiprocessor computer system
KR890017609A (ko) 멀티프로세서 데이타 처리시스템 및 그것에 사용되는 캐시장치
KR920000040A (ko) 카피-백 데이타 캐시를 구비한 데이타 치리기
US5408636A (en) System for flushing first and second caches upon detection of a write operation to write protected areas
DE69423938D1 (de) Datenverarbeitungssystem mit Aufrechterhaltung der Cachespeicherkohärenz unter Verwendung eines Snoopprotokolls
US5829027A (en) Removable processor board having first, second and third level cache system for use in a multiprocessor computer system
US5590310A (en) Method and structure for data integrity in a multiple level cache system
US5835934A (en) Method and apparatus of low power cache operation with a tag hit enablement
EP0285346A3 (de) Cache-Speichervorrichtung
EP0309995B1 (de) System zur schnellen Auswahl von nicht-cachespeicherbaren Adressenbereichen mittels einer programmierbaren Logikmatrix
JPH0797352B2 (ja) コンピュータ・システム及び入出力コントローラ
US5890216A (en) Apparatus and method for decreasing the access time to non-cacheable address space in a computer system
CA2148186A1 (en) Processor board having a second level writeback cache system and a third level writethrough cache system which stores exclusive state information for use in a multiprocessor computer system
EP0196244A3 (de) Anordnung von Cachespeicherverwaltungseinheiten
JP3013631B2 (ja) キャッシュメモリ同期方法
US5611072A (en) Cache with an extended single cycle read/write system and method
DE69433147D1 (de) Symmetrisches Mehrprozessorsystem mit vereinheitlichter Umgebung und verteilten Systemfunktionen
US5813028A (en) Cache read miss request invalidation prevention method
US7035981B1 (en) Asynchronous input/output cache having reduced latency
JPH04306750A (ja) マルチプロセッサシステム
KR100261587B1 (ko) 듀플리케이트 디렉터리의 캐시 적중 판단장치
KR940009853A (ko) 주행정 전산망시스템(ticom)의 캐시응집을 위한 버스동작 제어방법
KR970071241A (ko) 다중처리 시스템의 캐시 스테이트 램(ram) 관리방법

Legal Events

Date Code Title Description
8339 Ceased/non-payment of the annual fee