FR2864730B1 - Dispositif de memorisation - Google Patents

Dispositif de memorisation

Info

Publication number
FR2864730B1
FR2864730B1 FR0351208A FR0351208A FR2864730B1 FR 2864730 B1 FR2864730 B1 FR 2864730B1 FR 0351208 A FR0351208 A FR 0351208A FR 0351208 A FR0351208 A FR 0351208A FR 2864730 B1 FR2864730 B1 FR 2864730B1
Authority
FR
France
Prior art keywords
memorization device
memorization
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR0351208A
Other languages
English (en)
Other versions
FR2864730A1 (fr
Inventor
Christian Francois
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Temento Systems
Original Assignee
Temento Systems
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Temento Systems filed Critical Temento Systems
Priority to FR0351208A priority Critical patent/FR2864730B1/fr
Priority to US11/018,876 priority patent/US20050190876A1/en
Publication of FR2864730A1 publication Critical patent/FR2864730A1/fr
Application granted granted Critical
Publication of FR2864730B1 publication Critical patent/FR2864730B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
FR0351208A 2003-12-26 2003-12-26 Dispositif de memorisation Expired - Fee Related FR2864730B1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FR0351208A FR2864730B1 (fr) 2003-12-26 2003-12-26 Dispositif de memorisation
US11/018,876 US20050190876A1 (en) 2003-12-26 2004-12-21 Storing device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0351208A FR2864730B1 (fr) 2003-12-26 2003-12-26 Dispositif de memorisation

Publications (2)

Publication Number Publication Date
FR2864730A1 FR2864730A1 (fr) 2005-07-01
FR2864730B1 true FR2864730B1 (fr) 2006-03-17

Family

ID=34639761

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0351208A Expired - Fee Related FR2864730B1 (fr) 2003-12-26 2003-12-26 Dispositif de memorisation

Country Status (2)

Country Link
US (1) US20050190876A1 (fr)
FR (1) FR2864730B1 (fr)

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3679915A (en) * 1971-03-04 1972-07-25 Ibm Polarity hold latch with common data input-output terminal
US4841178A (en) * 1988-02-23 1989-06-20 Northern Telecom Limited Asynchronous processor arbitration circuit
DE3813427C1 (en) * 1988-04-18 1989-07-06 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt, De Failsafe memory circuit
US4973860A (en) * 1989-05-02 1990-11-27 Ast Research Inc. Circuit for synchronizing an asynchronous input signal to a high frequency clock
US5047658A (en) * 1990-06-01 1991-09-10 Ncr Corporation High frequency asynchronous data synchronizer
US5649163A (en) * 1992-10-29 1997-07-15 Altera Corporation Method of programming an asynchronous load storage device using a representation of a clear/preset storage device
US5526512A (en) * 1993-09-20 1996-06-11 International Business Machines Corporation Dynamic management of snoop granularity for a coherent asynchronous DMA cache
FR2727783B1 (fr) * 1994-12-05 1997-01-31 Suisse Electronique Microtech Element de memoire statique du type bascule latch
US5548622A (en) * 1995-03-24 1996-08-20 Sgs-Thomson Microelectronics, Inc. Method and structure for synchronization of asynchronous signals
DE19601370C1 (de) * 1996-01-16 1997-06-12 Siemens Ag Statische Halteglieder mit einphasigem Steuersignal
EP1122734B1 (fr) * 2000-01-31 2005-03-30 STMicroelectronics S.r.l. Mémoire entrelacée avec accès en rafale durant les phases de lecture synchrone dont les deux sous-matrices sont lisibles indépendamment lors d'un accès aléatoire durant les phases de lecture asynchrones

Also Published As

Publication number Publication date
FR2864730A1 (fr) 2005-07-01
US20050190876A1 (en) 2005-09-01

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Legal Events

Date Code Title Description
ST Notification of lapse

Effective date: 20090831