ES2088957T3 - Metodo para allanar una estructura de circuito integrado. - Google Patents

Metodo para allanar una estructura de circuito integrado.

Info

Publication number
ES2088957T3
ES2088957T3 ES90203417T ES90203417T ES2088957T3 ES 2088957 T3 ES2088957 T3 ES 2088957T3 ES 90203417 T ES90203417 T ES 90203417T ES 90203417 T ES90203417 T ES 90203417T ES 2088957 T3 ES2088957 T3 ES 2088957T3
Authority
ES
Spain
Prior art keywords
planarizing
layer
integrated circuit
circuit structure
low melting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES90203417T
Other languages
English (en)
Inventor
Jeffrey Marks
Kam Shing Law
David Nin-Kou Wang
Dan Maydan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Applied Materials Inc
Original Assignee
Applied Materials Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Applied Materials Inc filed Critical Applied Materials Inc
Application granted granted Critical
Publication of ES2088957T3 publication Critical patent/ES2088957T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H01L21/31055—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)
  • Drying Of Semiconductors (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

SE DESCRIBE UN PROCESO DE PLANARIZACION PARA PLANARIZAR UNA ESTRUCTURA DE CIRCUITO INTEGRADO (10) USANDO UN MATERIAL DE PLANARIZACION INORGANICA DE BAJA FUSION (30) QUE CONSISTE EN DEPOSITAR UNA CAPA DE PLANARIZACION INORGANICA DE FUSION BAJA (3) TAL COMO UN CRISTAL DE OXIDO DE BORO SOBRE UNA CAPA DE MATERIAL AISLANTE (20) TAL COMO UN OXIDO DE SILICONA Y DESPUES EL GRABADO EN SECO DE LA CAPA DE PLANARIZACION INORGANICA DE BAJA FUSION (3) PARA PLANARIZAR LA ESTRUCTURA. EL METODO ELIMINA LA NECESIDAD DE LOS PASOS DE RECUBRIMIENTO, SECADO, Y CURA SEPARADOS ASOCIADOS CON LA APLICACION DE CAPAS DE PLANARIZACION DE BASE ORGANICA NORMALMENTE REALIZADAS FUERA DE UN APARATO DE VACIO. EN UNA VERSION PREFERIDA, LOS PASOS DE DEPOSICION Y DE GRABADO SE REALIZAN SIN QUITAR LA ESTRUCTURA DE CIRCUITO INTEGRADO DEL APARATO DE VACIO. PUEDE REALIZARSE UN PASO DE GRABADO ADICIONAL DESPUES DE DEPOSITAR LA CAPA AISLANTE (20) PARA ELIMINAR CUALQUIER VACIO FORMADO EN LA CAPA AISLANTE (20).
ES90203417T 1988-11-10 1989-10-24 Metodo para allanar una estructura de circuito integrado. Expired - Lifetime ES2088957T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US26950888A 1988-11-10 1988-11-10

Publications (1)

Publication Number Publication Date
ES2088957T3 true ES2088957T3 (es) 1996-10-01

Family

ID=23027564

Family Applications (2)

Application Number Title Priority Date Filing Date
ES90203418T Expired - Lifetime ES2088958T3 (es) 1988-11-10 1989-10-24 Metodo para el aplanamiento de una estructura integrada.
ES90203417T Expired - Lifetime ES2088957T3 (es) 1988-11-10 1989-10-24 Metodo para allanar una estructura de circuito integrado.

Family Applications Before (1)

Application Number Title Priority Date Filing Date
ES90203418T Expired - Lifetime ES2088958T3 (es) 1988-11-10 1989-10-24 Metodo para el aplanamiento de una estructura integrada.

Country Status (5)

Country Link
EP (1) EP0368504A3 (es)
JP (1) JPH02199831A (es)
AT (2) ATE137608T1 (es)
DE (2) DE68926344T2 (es)
ES (2) ES2088958T3 (es)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU5281690A (en) * 1989-02-21 1990-09-26 Lam Research Corporation Novel glass deposition viscoelastic flow process
JPH0774146A (ja) * 1990-02-09 1995-03-17 Applied Materials Inc 低融点無機材料を使用する集積回路構造の改良された平坦化方法
JP3092185B2 (ja) * 1990-07-30 2000-09-25 セイコーエプソン株式会社 半導体装置の製造方法
KR0182006B1 (ko) * 1995-11-10 1999-04-15 김광호 반도체 패키지 장치 및 몰딩물질에 의해 발생하는 기생용량의 산출방법
KR102391994B1 (ko) * 2017-08-14 2022-04-28 삼성디스플레이 주식회사 멀티 스택 접합체, 멀티 스택 접합체의 제조 방법 및 멀티 스택 접합체를 포함하는 표시 장치

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2961350A (en) * 1958-04-28 1960-11-22 Bell Telephone Labor Inc Glass coating of circuit elements
US3755720A (en) * 1972-09-25 1973-08-28 Rca Corp Glass encapsulated semiconductor device
DE2713647C2 (de) * 1977-03-28 1984-11-29 Tokyo Shibaura Electric Co., Ltd., Kawasaki, Kanagawa Halbleitervorrichtung, bestehend aus einem Halbleitersubstrat und aus einem Oberflächenschutzfilm
IE52971B1 (en) * 1979-07-23 1988-04-27 Fujitsu Ltd Method of manufacturing a semiconductor device wherein first and second layers are formed
JPS5648140A (en) * 1979-09-27 1981-05-01 Seiko Epson Corp Manufacture of semiconductor device
US4407851A (en) * 1981-04-13 1983-10-04 Tokyo Shibaura Denki Kabushiki Kaisha Method for manufacturing semiconductor device
JPS5834945A (ja) * 1981-08-26 1983-03-01 Nippon Telegr & Teleph Corp <Ntt> 多層配線構造体
JPS58190043A (ja) * 1982-04-30 1983-11-05 Seiko Epson Corp 多層配線法
JPS58210634A (ja) * 1982-05-31 1983-12-07 Toshiba Corp 半導体装置の製造方法
JPS62169442A (ja) * 1986-01-22 1987-07-25 Nec Corp 素子分離領域の形成方法

Also Published As

Publication number Publication date
DE68926344T2 (de) 1996-09-05
ES2088958T3 (es) 1996-10-01
DE68926392D1 (de) 1996-06-05
DE68926344D1 (de) 1996-05-30
ATE137608T1 (de) 1996-05-15
JPH02199831A (ja) 1990-08-08
DE68926392T2 (de) 1996-08-14
EP0368504A2 (en) 1990-05-16
ATE137358T1 (de) 1996-05-15
EP0368504A3 (en) 1990-09-12

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