ES2078245T3 - Ram de doble puerto. - Google Patents

Ram de doble puerto.

Info

Publication number
ES2078245T3
ES2078245T3 ES89312592T ES89312592T ES2078245T3 ES 2078245 T3 ES2078245 T3 ES 2078245T3 ES 89312592 T ES89312592 T ES 89312592T ES 89312592 T ES89312592 T ES 89312592T ES 2078245 T3 ES2078245 T3 ES 2078245T3
Authority
ES
Spain
Prior art keywords
portions
memory location
port ram
double port
allowing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES89312592T
Other languages
English (en)
Inventor
Iii Rudolph Joseph Albachten
Robert William O'dell
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of ES2078245T3 publication Critical patent/ES2078245T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups

Abstract

UN DISPOSITIVO DE MEMORIA DE ACCESO ALEATORIO DE PUERTO DOBLE, QUE TIENE UNA POSICION DE MEMORIA LA CUAL TIENE INTERFACES PARA PERMITIR POR LO MENOS QUE DOS DISPOSITIVOS TENGAN ACCESO A UNA POSICION DADA DE LA MEMORIA. LA POSICION DE LA MEMORIA SE SUBDIVIDE EN, POR LO MENOS, DOS PORCIONES. UNA DE ELLAS ES UNA FUENTE U ORIGEN Y LA OTRA UN DESTINO. SE DISPONE DE UN MECANISMO DE ACTUALIZACION DE SOMBRAS, Y ESTA CONECTADO A CADA UNA DE LAS PORCIONES DE POSICION DE MEMORIA PARA PERMITIR QUE LOS DATOS ALMACENADOS EN UNA DE LAS PORCIONES SE COPIE EN LA OTRA PORCION.
ES89312592T 1988-12-19 1989-12-01 Ram de doble puerto. Expired - Lifetime ES2078245T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/286,200 US5014247A (en) 1988-12-19 1988-12-19 System for accessing the same memory location by two different devices

Publications (1)

Publication Number Publication Date
ES2078245T3 true ES2078245T3 (es) 1995-12-16

Family

ID=23097531

Family Applications (1)

Application Number Title Priority Date Filing Date
ES89312592T Expired - Lifetime ES2078245T3 (es) 1988-12-19 1989-12-01 Ram de doble puerto.

Country Status (7)

Country Link
US (1) US5014247A (es)
EP (1) EP0375194B1 (es)
JP (1) JP2821534B2 (es)
AT (1) ATE126922T1 (es)
DE (1) DE68923944T2 (es)
ES (1) ES2078245T3 (es)
GR (1) GR3017876T3 (es)

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5247649A (en) * 1988-05-06 1993-09-21 Hitachi, Ltd. Multi-processor system having a multi-port cache memory
JPH03219345A (ja) * 1990-01-25 1991-09-26 Toshiba Corp 多ポートキャッシュメモリ制御装置
US5341473A (en) * 1990-08-09 1994-08-23 Nec Corporation System of transferring data in a multi-CPU arrangement using address generators
US5826101A (en) * 1990-09-28 1998-10-20 Texas Instruments Incorporated Data processing device having split-mode DMA channel
US5249283A (en) * 1990-12-24 1993-09-28 Ncr Corporation Cache coherency method and apparatus for a multiple path interconnection network
GB9101227D0 (en) * 1991-01-19 1991-02-27 Lucas Ind Plc Method of and apparatus for arbitrating between a plurality of controllers,and control system
FR2672140B1 (fr) * 1991-01-28 1996-08-30 Bosch Gmbh Robert Systeme a multicalculateur.
DE4129809C2 (de) * 1991-01-28 2000-08-17 Bosch Gmbh Robert Mehrrechnersystem
JPH04257048A (ja) * 1991-02-12 1992-09-11 Mitsubishi Electric Corp デュアルポートメモリ
JP2673390B2 (ja) * 1991-03-13 1997-11-05 三菱電機株式会社 マルチポートメモリ
JP3169639B2 (ja) * 1991-06-27 2001-05-28 日本電気株式会社 半導体記憶装置
US5289427A (en) * 1992-07-20 1994-02-22 Motorola, Inc. Multiport memory with write priority detector
USRE39116E1 (en) 1992-11-02 2006-06-06 Negotiated Data Solutions Llc Network link detection and generation
USRE39395E1 (en) 1992-11-02 2006-11-14 Negotiated Data Solutions Llc Data communication network with transfer port, cascade port and/or frame synchronizing signal
EP0596651A1 (en) * 1992-11-02 1994-05-11 National Semiconductor Corporation Network for data communication with isochronous capability
EP0596648A1 (en) 1992-11-02 1994-05-11 National Semiconductor Corporation Network link endpoint capability detection
US5581720A (en) * 1994-04-15 1996-12-03 David Sarnoff Research Center, Inc. Apparatus and method for updating information in a microcode instruction
US5533018A (en) 1994-12-21 1996-07-02 National Semiconductor Corporation Multi-protocol packet framing over an isochronous network
JPH1027150A (ja) 1996-07-09 1998-01-27 Murata Mach Ltd 情報処理装置及び外部装置
DE19909081C2 (de) * 1999-03-02 2003-03-20 Siemens Ag Anordnung zur Übertragung von in mehrere Wörter unterteilten Datensätzen
DE10060124A1 (de) * 2000-12-04 2002-06-13 Siemens Ag Verfahren zum Betrieb eines Datenverarbeitungssystems
US6980481B1 (en) * 2001-12-20 2005-12-27 Lsi Logic Corporatiion Address transition detect control circuit for self timed asynchronous memories
GB0203070D0 (en) * 2002-02-09 2002-03-27 Qinetiq Ltd Multiple write-port memory
US7788669B2 (en) * 2003-05-02 2010-08-31 Microsoft Corporation System for isolating first computing environment from second execution environment while sharing resources by copying data from first portion to second portion of memory
US7483313B2 (en) * 2007-01-31 2009-01-27 Dell Products, Lp Dual ported memory with selective read and write protection
US20080235477A1 (en) * 2007-03-19 2008-09-25 Rawson Andrew R Coherent data mover
US8359437B2 (en) * 2008-05-13 2013-01-22 International Business Machines Corporation Virtual computing memory stacking
US9870318B2 (en) 2014-07-23 2018-01-16 Advanced Micro Devices, Inc. Technique to improve performance of memory copies and stores

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4125877A (en) * 1976-11-26 1978-11-14 Motorola, Inc. Dual port random access memory storage cell
JPS59142799A (ja) * 1983-02-04 1984-08-16 Hitachi Ltd バツクアツプ用蓄電装置付二重化記憶装置
DE3881222D1 (de) * 1987-01-23 1993-07-01 Siemens Ag Halbleiterspeicher mit wahlfreiem zugriff ueber zwei getrennte ein/ausgaenge.

Also Published As

Publication number Publication date
ATE126922T1 (de) 1995-09-15
EP0375194B1 (en) 1995-08-23
JP2821534B2 (ja) 1998-11-05
DE68923944D1 (de) 1995-09-28
EP0375194A2 (en) 1990-06-27
DE68923944T2 (de) 1996-04-11
EP0375194A3 (en) 1991-09-04
JPH02246092A (ja) 1990-10-01
US5014247A (en) 1991-05-07
GR3017876T3 (en) 1996-01-31

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