DE69229988D1 - Kombinierte DRAM- und SRAM-Speichermatrize - Google Patents

Kombinierte DRAM- und SRAM-Speichermatrize

Info

Publication number
DE69229988D1
DE69229988D1 DE69229988T DE69229988T DE69229988D1 DE 69229988 D1 DE69229988 D1 DE 69229988D1 DE 69229988 T DE69229988 T DE 69229988T DE 69229988 T DE69229988 T DE 69229988T DE 69229988 D1 DE69229988 D1 DE 69229988D1
Authority
DE
Germany
Prior art keywords
sram memory
memory matrix
combined dram
dram
combined
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69229988T
Other languages
English (en)
Other versions
DE69229988T2 (de
Inventor
David B Scott
Hiep V Tran
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Application granted granted Critical
Publication of DE69229988D1 publication Critical patent/DE69229988D1/de
Publication of DE69229988T2 publication Critical patent/DE69229988T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/106—Data output latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/005—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10—Aspects relating to interfaces of memory device to external buses
    • G11C2207/108—Wide data ports

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Databases & Information Systems (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
DE69229988T 1991-12-23 1992-12-23 Kombinierte DRAM- und SRAM-Speichermatrize Expired - Fee Related DE69229988T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/812,676 US5291444A (en) 1991-12-23 1991-12-23 Combination DRAM and SRAM memory array

Publications (2)

Publication Number Publication Date
DE69229988D1 true DE69229988D1 (de) 1999-10-21
DE69229988T2 DE69229988T2 (de) 2000-02-24

Family

ID=25210310

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69229988T Expired - Fee Related DE69229988T2 (de) 1991-12-23 1992-12-23 Kombinierte DRAM- und SRAM-Speichermatrize

Country Status (5)

Country Link
US (1) US5291444A (de)
EP (1) EP0548964B1 (de)
JP (1) JPH05347092A (de)
DE (1) DE69229988T2 (de)
TW (1) TW212848B (de)

Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5226147A (en) 1987-11-06 1993-07-06 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device for simple cache system
US5652723A (en) * 1991-04-18 1997-07-29 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device
US5550782A (en) * 1991-09-03 1996-08-27 Altera Corporation Programmable logic array integrated circuits
DE69521741T2 (de) * 1994-05-03 2002-05-23 Sun Microsystems Inc Direktzugriffspeicher und System für Rasterpuffer
US5521880A (en) * 1994-05-31 1996-05-28 Sgs-Thomson Microelectronics, Inc. Integrated circuit memory having control circuitry for shared data bus
US5748633A (en) * 1995-07-12 1998-05-05 3Com Corporation Method and apparatus for the concurrent reception and transmission of packets in a communications internetworking device
US5825774A (en) * 1995-07-12 1998-10-20 3Com Corporation Packet characterization using code vectors
US5651002A (en) * 1995-07-12 1997-07-22 3Com Corporation Internetworking device with enhanced packet header translation and memory
US5812775A (en) * 1995-07-12 1998-09-22 3Com Corporation Method and apparatus for internetworking buffer management
US5796944A (en) * 1995-07-12 1998-08-18 3Com Corporation Apparatus and method for processing data frames in an internetworking device
KR100224769B1 (ko) * 1995-12-29 1999-10-15 김영환 고속 버스트 리드/라이트 동작에 적합한 데이타 버스 라인 구조를 갖는 반도체 메모리 장치
US6209071B1 (en) * 1996-05-07 2001-03-27 Rambus Inc. Asynchronous request/synchronous data dynamic random access memory
US5748547A (en) * 1996-05-24 1998-05-05 Shau; Jeng-Jye High performance semiconductor memory devices having multiple dimension bit lines
US6167486A (en) * 1996-11-18 2000-12-26 Nec Electronics, Inc. Parallel access virtual channel memory system with cacheable channels
US5748554A (en) * 1996-12-20 1998-05-05 Rambus, Inc. Memory and method for sensing sub-groups of memory elements
JP3161385B2 (ja) * 1997-09-16 2001-04-25 日本電気株式会社 半導体記憶装置
WO1999019874A1 (en) 1997-10-10 1999-04-22 Rambus Incorporated Power control system for synchronous memory device
US6467017B1 (en) 1998-06-23 2002-10-15 Altera Corporation Programmable logic device having embedded dual-port random access memory configurable as single-port memory
US6141235A (en) * 1998-07-31 2000-10-31 Texas Instruments Incorporated Stacked cache memory system and method
US6094393A (en) * 1999-07-29 2000-07-25 Texas Instruments Incorporated Stacked sense-amp cache memory system and method
US6708254B2 (en) 1999-11-10 2004-03-16 Nec Electronics America, Inc. Parallel access virtual channel memory system
US7500075B1 (en) * 2001-04-17 2009-03-03 Rambus Inc. Mechanism for enabling full data bus utilization without increasing data granularity
US6825841B2 (en) * 2001-09-07 2004-11-30 Rambus Inc. Granularity memory column access
US7111110B1 (en) 2002-12-10 2006-09-19 Altera Corporation Versatile RAM for programmable logic device
US8190808B2 (en) * 2004-08-17 2012-05-29 Rambus Inc. Memory device having staggered memory operations
US7280428B2 (en) 2004-09-30 2007-10-09 Rambus Inc. Multi-column addressing mode memory system including an integrated circuit memory device
US8595459B2 (en) * 2004-11-29 2013-11-26 Rambus Inc. Micro-threaded memory
US20070260841A1 (en) 2006-05-02 2007-11-08 Hampel Craig E Memory module with reduced access granularity
US9268719B2 (en) 2011-08-05 2016-02-23 Rambus Inc. Memory signal buffers and modules supporting variable access granularity
US8593860B2 (en) 2011-12-09 2013-11-26 Gsi Technology, Inc. Systems and methods of sectioned bit line memory arrays
US8693236B2 (en) 2011-12-09 2014-04-08 Gsi Technology, Inc. Systems and methods of sectioned bit line memory arrays, including hierarchical and/or other features
US9165650B2 (en) 2013-02-07 2015-10-20 Qualcomm Incorporated Hybrid dynamic-static encoder with optional hit and/or multi-hit detection

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH069114B2 (ja) * 1983-06-24 1994-02-02 株式会社東芝 半導体メモリ
JPS6180597A (ja) * 1984-09-26 1986-04-24 Hitachi Ltd 半導体記憶装置
JPH0793009B2 (ja) * 1984-12-13 1995-10-09 株式会社東芝 半導体記憶装置
JPS62287497A (ja) * 1986-06-06 1987-12-14 Fujitsu Ltd 半導体記憶装置
JP2591010B2 (ja) * 1988-01-29 1997-03-19 日本電気株式会社 シリアルアクセスメモリ装置
JPH07109702B2 (ja) * 1988-09-12 1995-11-22 株式会社東芝 ダイナミック型メモリ
KR920001075B1 (ko) * 1989-09-08 1992-02-01 현대전자산업 주식회사 다이나믹램의 센스 증폭기용 래칭부

Also Published As

Publication number Publication date
JPH05347092A (ja) 1993-12-27
EP0548964A2 (de) 1993-06-30
DE69229988T2 (de) 2000-02-24
EP0548964A3 (en) 1994-08-10
US5291444A (en) 1994-03-01
TW212848B (de) 1993-09-11
EP0548964B1 (de) 1999-09-15

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee