DE68921332T2 - Rechneranordnungen mit Ein-/Ausgabecachespeicher. - Google Patents

Rechneranordnungen mit Ein-/Ausgabecachespeicher.

Info

Publication number
DE68921332T2
DE68921332T2 DE68921332T DE68921332T DE68921332T2 DE 68921332 T2 DE68921332 T2 DE 68921332T2 DE 68921332 T DE68921332 T DE 68921332T DE 68921332 T DE68921332 T DE 68921332T DE 68921332 T2 DE68921332 T2 DE 68921332T2
Authority
DE
Germany
Prior art keywords
input
cache memory
output cache
computer arrangements
arrangements
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68921332T
Other languages
English (en)
Other versions
DE68921332D1 (de
Inventor
James Otto Nicholson
John Claude O'quin
John Thomas O'quin
Frederick Ernest Strietelmeier
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE68921332D1 publication Critical patent/DE68921332D1/de
Publication of DE68921332T2 publication Critical patent/DE68921332T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0846—Cache with multiple tag or data arrays being simultaneously accessible
    • G06F12/0848—Partitioned cache, e.g. separate instruction and operand caches
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/084—Multiuser, multiprocessor or multiprocessing cache systems with a shared cache
DE68921332T 1989-01-13 1989-12-11 Rechneranordnungen mit Ein-/Ausgabecachespeicher. Expired - Fee Related DE68921332T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US29777589A 1989-01-13 1989-01-13

Publications (2)

Publication Number Publication Date
DE68921332D1 DE68921332D1 (de) 1995-03-30
DE68921332T2 true DE68921332T2 (de) 1995-08-10

Family

ID=23147692

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68921332T Expired - Fee Related DE68921332T2 (de) 1989-01-13 1989-12-11 Rechneranordnungen mit Ein-/Ausgabecachespeicher.

Country Status (3)

Country Link
EP (1) EP0377969B1 (de)
JP (1) JPH087663B2 (de)
DE (1) DE68921332T2 (de)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4796346B2 (ja) * 2004-07-28 2011-10-19 ルネサスエレクトロニクス株式会社 マイクロコンピュータ

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5547523A (en) * 1978-09-28 1980-04-04 Toshiba Corp Input and output processing device
JPS6053342B2 (ja) * 1982-04-16 1985-11-25 株式会社日立製作所 情報伝送方式
US4685082A (en) * 1985-02-22 1987-08-04 Wang Laboratories, Inc. Simplified cache with automatic update
JPS6368957A (ja) * 1986-09-10 1988-03-28 Fuji Electric Co Ltd 情報処理装置におけるデ−タ転送方式

Also Published As

Publication number Publication date
JPH087663B2 (ja) 1996-01-29
JPH02226447A (ja) 1990-09-10
EP0377969B1 (de) 1995-02-22
EP0377969A2 (de) 1990-07-18
EP0377969A3 (de) 1991-03-20
DE68921332D1 (de) 1995-03-30

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee