JPS5547523A - Input and output processing device - Google Patents

Input and output processing device

Info

Publication number
JPS5547523A
JPS5547523A JP11860078A JP11860078A JPS5547523A JP S5547523 A JPS5547523 A JP S5547523A JP 11860078 A JP11860078 A JP 11860078A JP 11860078 A JP11860078 A JP 11860078A JP S5547523 A JPS5547523 A JP S5547523A
Authority
JP
Japan
Prior art keywords
bus
cpu
control portion
input
firmware
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11860078A
Other languages
Japanese (ja)
Inventor
Shuji Murakami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP11860078A priority Critical patent/JPS5547523A/en
Publication of JPS5547523A publication Critical patent/JPS5547523A/en
Pending legal-status Critical Current

Links

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  • Bus Control (AREA)

Abstract

PURPOSE: To preferentially carry out the data transmission in which the speed is requested and perform the interrupt processing with flexibility by and alotting the functions for hardware and firmware in the case of connecting the input and output devices different in bus interface to the information processing system.
CONSTITUTION: The adpter 21 is an interface controller of the bus of a machine type controlled by the microcomputer and the other bus of the other machine type and mainly comprises a control portion μ CPU 22 constituting a base of the adapter, ROM23 for accommodating the firmware therein, command from CPU, RAM 24 for retracting the interruption from IO, bus control portion BCA 25 for carrying out the dialog with CPU, and bus control portion BCN 26 for carrying out the bus dialog with IO.
COPYRIGHT: (C)1980,JPO&Japio
JP11860078A 1978-09-28 1978-09-28 Input and output processing device Pending JPS5547523A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11860078A JPS5547523A (en) 1978-09-28 1978-09-28 Input and output processing device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11860078A JPS5547523A (en) 1978-09-28 1978-09-28 Input and output processing device

Publications (1)

Publication Number Publication Date
JPS5547523A true JPS5547523A (en) 1980-04-04

Family

ID=14740576

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11860078A Pending JPS5547523A (en) 1978-09-28 1978-09-28 Input and output processing device

Country Status (1)

Country Link
JP (1) JPS5547523A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5840645A (en) * 1981-09-04 1983-03-09 Fujitsu Ltd Input and output control system
JPH02226447A (en) * 1989-01-13 1990-09-10 Internatl Business Mach Corp <Ibm> Computer system and memory access therefor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5840645A (en) * 1981-09-04 1983-03-09 Fujitsu Ltd Input and output control system
JPH02226447A (en) * 1989-01-13 1990-09-10 Internatl Business Mach Corp <Ibm> Computer system and memory access therefor

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