NO892310D0 - Anordning og fremgangsmaate for aa oeke virtuell til reell adressetranslasjon for aksessering av et cache-lager. - Google Patents

Anordning og fremgangsmaate for aa oeke virtuell til reell adressetranslasjon for aksessering av et cache-lager.

Info

Publication number
NO892310D0
NO892310D0 NO892310A NO892310A NO892310D0 NO 892310 D0 NO892310 D0 NO 892310D0 NO 892310 A NO892310 A NO 892310A NO 892310 A NO892310 A NO 892310A NO 892310 D0 NO892310 D0 NO 892310D0
Authority
NO
Norway
Prior art keywords
cache
accessing
stock
procedure
development
Prior art date
Application number
NO892310A
Other languages
English (en)
Other versions
NO892310L (no
NO176633B (no
NO176633C (no
Inventor
Leonard Rabins
Original Assignee
Bull Hn Information Syst
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Bull Hn Information Syst filed Critical Bull Hn Information Syst
Publication of NO892310D0 publication Critical patent/NO892310D0/no
Publication of NO892310L publication Critical patent/NO892310L/no
Publication of NO176633B publication Critical patent/NO176633B/no
Publication of NO176633C publication Critical patent/NO176633C/no

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1045—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
    • G06F12/1054—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache the data cache being concurrently physically addressed
NO892310A 1988-06-07 1989-06-06 Anordning og fremgangsmåte for å öke virtuell til reell adressetranslasjon for aksessering av et midlertidig hurtiglager NO176633C (no)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US20349088A 1988-06-07 1988-06-07

Publications (4)

Publication Number Publication Date
NO892310D0 true NO892310D0 (no) 1989-06-06
NO892310L NO892310L (no) 1989-12-08
NO176633B NO176633B (no) 1995-01-23
NO176633C NO176633C (no) 1995-05-03

Family

ID=22754220

Family Applications (1)

Application Number Title Priority Date Filing Date
NO892310A NO176633C (no) 1988-06-07 1989-06-06 Anordning og fremgangsmåte for å öke virtuell til reell adressetranslasjon for aksessering av et midlertidig hurtiglager

Country Status (13)

Country Link
EP (1) EP0349757B1 (no)
JP (1) JPH0251755A (no)
KR (1) KR930002314B1 (no)
CN (1) CN1024600C (no)
AU (1) AU612035B2 (no)
CA (1) CA1328026C (no)
DE (1) DE68926837T2 (no)
ES (1) ES2090023T3 (no)
FI (1) FI96645C (no)
HR (1) HRP921095A2 (no)
MX (1) MX173010B (no)
NO (1) NO176633C (no)
YU (1) YU117089A (no)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6965922B1 (en) * 2000-04-18 2005-11-15 International Business Machines Corporation Computer system and method with internal use of networking switching
US7146484B2 (en) 2004-06-15 2006-12-05 Hitachi, Ltd. Method and apparatus for caching storage system

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51140521A (en) * 1975-05-30 1976-12-03 Nec Corp Address exchange device
JPS51145227A (en) * 1975-06-09 1976-12-14 Nec Corp Buffer memory system
US4170039A (en) * 1978-07-17 1979-10-02 International Business Machines Corporation Virtual address translation speed up technique
JPS5696334A (en) * 1979-12-28 1981-08-04 Fujitsu Ltd Prefetch system
US4332010A (en) * 1980-03-17 1982-05-25 International Business Machines Corporation Cache synonym detection and handling mechanism
JPS6049944B2 (ja) * 1980-12-29 1985-11-06 富士通株式会社 バッファ記憶制御方式
US4400774A (en) * 1981-02-02 1983-08-23 Bell Telephone Laboratories, Incorporated Cache addressing arrangement in a computer system
JPS5975482A (ja) * 1982-10-22 1984-04-28 Fujitsu Ltd バツフア・ストレ−ジ制御方式
EP0206050A3 (en) * 1985-06-28 1990-03-14 Hewlett-Packard Company Virtually addressed cache memory with physical tags

Also Published As

Publication number Publication date
KR900000773A (ko) 1990-01-31
YU117089A (sh) 1992-07-20
NO892310L (no) 1989-12-08
EP0349757A3 (en) 1990-09-19
CN1024600C (zh) 1994-05-18
CA1328026C (en) 1994-03-22
NO176633B (no) 1995-01-23
HRP921095A2 (hr) 1994-04-30
NO176633C (no) 1995-05-03
FI892779A0 (fi) 1989-06-07
FI96645B (fi) 1996-04-15
CN1040446A (zh) 1990-03-14
EP0349757A2 (en) 1990-01-10
DE68926837T2 (de) 1997-03-06
KR930002314B1 (ko) 1993-03-29
AU612035B2 (en) 1991-06-27
FI96645C (fi) 1996-07-25
JPH0251755A (ja) 1990-02-21
EP0349757B1 (en) 1996-07-17
DE68926837D1 (de) 1996-08-22
ES2090023T3 (es) 1996-10-16
FI892779A (fi) 1989-12-08
AU3592489A (en) 1989-12-14
MX173010B (es) 1994-01-28

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