ATE126922T1 - Ram mit doppelten ein/ausgängen. - Google Patents

Ram mit doppelten ein/ausgängen.

Info

Publication number
ATE126922T1
ATE126922T1 AT89312592T AT89312592T ATE126922T1 AT E126922 T1 ATE126922 T1 AT E126922T1 AT 89312592 T AT89312592 T AT 89312592T AT 89312592 T AT89312592 T AT 89312592T AT E126922 T1 ATE126922 T1 AT E126922T1
Authority
AT
Austria
Prior art keywords
portions
memory location
ram
outputs
double
Prior art date
Application number
AT89312592T
Other languages
English (en)
Inventor
Iii Rudolph Joseph Albachten
Robert William O'dell
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of ATE126922T1 publication Critical patent/ATE126922T1/de

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
AT89312592T 1988-12-19 1989-12-01 Ram mit doppelten ein/ausgängen. ATE126922T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/286,200 US5014247A (en) 1988-12-19 1988-12-19 System for accessing the same memory location by two different devices

Publications (1)

Publication Number Publication Date
ATE126922T1 true ATE126922T1 (de) 1995-09-15

Family

ID=23097531

Family Applications (1)

Application Number Title Priority Date Filing Date
AT89312592T ATE126922T1 (de) 1988-12-19 1989-12-01 Ram mit doppelten ein/ausgängen.

Country Status (7)

Country Link
US (1) US5014247A (de)
EP (1) EP0375194B1 (de)
JP (1) JP2821534B2 (de)
AT (1) ATE126922T1 (de)
DE (1) DE68923944T2 (de)
ES (1) ES2078245T3 (de)
GR (1) GR3017876T3 (de)

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5247649A (en) * 1988-05-06 1993-09-21 Hitachi, Ltd. Multi-processor system having a multi-port cache memory
JPH03219345A (ja) * 1990-01-25 1991-09-26 Toshiba Corp 多ポートキャッシュメモリ制御装置
US5341473A (en) * 1990-08-09 1994-08-23 Nec Corporation System of transferring data in a multi-CPU arrangement using address generators
US5826101A (en) * 1990-09-28 1998-10-20 Texas Instruments Incorporated Data processing device having split-mode DMA channel
US5249283A (en) * 1990-12-24 1993-09-28 Ncr Corporation Cache coherency method and apparatus for a multiple path interconnection network
GB9101227D0 (en) * 1991-01-19 1991-02-27 Lucas Ind Plc Method of and apparatus for arbitrating between a plurality of controllers,and control system
DE4129809C2 (de) * 1991-01-28 2000-08-17 Bosch Gmbh Robert Mehrrechnersystem
FR2672140B1 (fr) * 1991-01-28 1996-08-30 Bosch Gmbh Robert Systeme a multicalculateur.
JPH04257048A (ja) * 1991-02-12 1992-09-11 Mitsubishi Electric Corp デュアルポートメモリ
JP2673390B2 (ja) * 1991-03-13 1997-11-05 三菱電機株式会社 マルチポートメモリ
JP3169639B2 (ja) * 1991-06-27 2001-05-28 日本電気株式会社 半導体記憶装置
US5289427A (en) * 1992-07-20 1994-02-22 Motorola, Inc. Multiport memory with write priority detector
EP0596651A1 (de) * 1992-11-02 1994-05-11 National Semiconductor Corporation Datennetz mit isochroner Übertragungsfähigkeit
USRE39116E1 (en) 1992-11-02 2006-06-06 Negotiated Data Solutions Llc Network link detection and generation
USRE39395E1 (en) 1992-11-02 2006-11-14 Negotiated Data Solutions Llc Data communication network with transfer port, cascade port and/or frame synchronizing signal
EP0596648A1 (de) 1992-11-02 1994-05-11 National Semiconductor Corporation Erkennung du Fähigkeiten eines Netzendpunkts
US5581720A (en) * 1994-04-15 1996-12-03 David Sarnoff Research Center, Inc. Apparatus and method for updating information in a microcode instruction
US5533018A (en) 1994-12-21 1996-07-02 National Semiconductor Corporation Multi-protocol packet framing over an isochronous network
JPH1027150A (ja) 1996-07-09 1998-01-27 Murata Mach Ltd 情報処理装置及び外部装置
DE19909081C2 (de) * 1999-03-02 2003-03-20 Siemens Ag Anordnung zur Übertragung von in mehrere Wörter unterteilten Datensätzen
DE10060124A1 (de) * 2000-12-04 2002-06-13 Siemens Ag Verfahren zum Betrieb eines Datenverarbeitungssystems
US6980481B1 (en) * 2001-12-20 2005-12-27 Lsi Logic Corporatiion Address transition detect control circuit for self timed asynchronous memories
GB0203070D0 (en) * 2002-02-09 2002-03-27 Qinetiq Ltd Multiple write-port memory
US7788669B2 (en) * 2003-05-02 2010-08-31 Microsoft Corporation System for isolating first computing environment from second execution environment while sharing resources by copying data from first portion to second portion of memory
US7483313B2 (en) * 2007-01-31 2009-01-27 Dell Products, Lp Dual ported memory with selective read and write protection
US20080235477A1 (en) * 2007-03-19 2008-09-25 Rawson Andrew R Coherent data mover
US8359437B2 (en) * 2008-05-13 2013-01-22 International Business Machines Corporation Virtual computing memory stacking
US9870318B2 (en) 2014-07-23 2018-01-16 Advanced Micro Devices, Inc. Technique to improve performance of memory copies and stores

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4125877A (en) * 1976-11-26 1978-11-14 Motorola, Inc. Dual port random access memory storage cell
JPS59142799A (ja) * 1983-02-04 1984-08-16 Hitachi Ltd バツクアツプ用蓄電装置付二重化記憶装置
EP0275884B1 (de) * 1987-01-23 1993-05-26 Siemens Aktiengesellschaft Halbleiterspeicher mit wahlfreiem Zugriff über zwei getrennte Ein/Ausgänge

Also Published As

Publication number Publication date
US5014247A (en) 1991-05-07
DE68923944D1 (de) 1995-09-28
JPH02246092A (ja) 1990-10-01
GR3017876T3 (en) 1996-01-31
EP0375194A3 (de) 1991-09-04
DE68923944T2 (de) 1996-04-11
EP0375194A2 (de) 1990-06-27
EP0375194B1 (de) 1995-08-23
JP2821534B2 (ja) 1998-11-05
ES2078245T3 (es) 1995-12-16

Similar Documents

Publication Publication Date Title
ATE126922T1 (de) Ram mit doppelten ein/ausgängen.
DE69033398T2 (de) Rechnerarchitektur mit Mehrfachbefehlsausgabe
DE3689488D1 (de) Speicheranordnung mit vereinfachtem und schnellem Daten-Cachespeicher.
AU530887B2 (en) Memory with parallel refresh operations
KR900008765A (ko) 단일 트랜지스터 메모리 셀과 함께 사용하는 고속차동 센스 증폭기
DE68927783D1 (de) Mikroprozessor mit äusserem steuerungsspeicher
DE3883865T2 (de) Halbleiterspeicheranordnung mit einem Register.
DE68921900T2 (de) Halbleiterspeicheranordnung mit serieller Zugriffsanordnung.
DE69025516D1 (de) Halbleiter-Speichergerät mit redundanten Speicherzellen
DE3850567T2 (de) DRAM-Zelle mit verstärkter Ladung.
NL193547B (nl) Halfgeleider-geheugenmatrix met reservegeheugenelementen.
DE3850705D1 (de) Beleuchtungseinrichtung mit grossem Fläche-zu-Dicke-Verhältnis und darin verwendete Folie.
DE68918894D1 (de) Statische MESFET-Speicherzelle mit wahlfreiem Zugriff.
DE68926759D1 (de) Steuerspeicher mit Schieberegistern
DE3853182T2 (de) Speicherzelle mit gesättigtem schnellem Schreiben.
DE69127782T2 (de) Speicherzugriffssteuerung mit gemeinsam genutzter Pipelinestruktur
DE3855298D1 (de) Microprozessor mit wortorganisiertem Datenspeicher
FR2617528B1 (fr) Fermeture anti-panique a condamnation active
FR2637917B1 (fr) Sechoir a double pietement repliable en v
DE68924896D1 (de) Cachespeicher mit mindestens zwei füllgrössen.
DE68924230D1 (de) Befehlscachespeicher mit flush-on-rei-steuerung.
KR900012275A (ko) 리프레시기능 개선형 반도체 기억장치
DE69007496D1 (de) Speicherzelle mit schreiblasttransistoren.
BR6800138U (pt) Envelope com fechamento rapido
DE68921332D1 (de) Rechneranordnungen mit Ein-/Ausgabecachespeicher.

Legal Events

Date Code Title Description
UEP Publication of translation of european patent specification
REN Ceased due to non-payment of the annual fee