DE68924896D1 - Cachespeicher mit mindestens zwei füllgrössen. - Google Patents

Cachespeicher mit mindestens zwei füllgrössen.

Info

Publication number
DE68924896D1
DE68924896D1 DE68924896T DE68924896T DE68924896D1 DE 68924896 D1 DE68924896 D1 DE 68924896D1 DE 68924896 T DE68924896 T DE 68924896T DE 68924896 T DE68924896 T DE 68924896T DE 68924896 D1 DE68924896 D1 DE 68924896D1
Authority
DE
Germany
Prior art keywords
cache storage
sizes
filling
filling sizes
cache
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68924896T
Other languages
English (en)
Other versions
DE68924896T2 (de
Inventor
Simon Steely
Raj Ramanujan
Peter Bannon
Walter Beach
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Digital Equipment Corp
Original Assignee
Digital Equipment Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Digital Equipment Corp filed Critical Digital Equipment Corp
Publication of DE68924896D1 publication Critical patent/DE68924896D1/de
Application granted granted Critical
Publication of DE68924896T2 publication Critical patent/DE68924896T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0842—Multiuser, multiprocessor or multiprocessing cache systems for multiprocessing or multitasking

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
DE68924896T 1988-04-01 1989-03-30 Cachespeicher mit mindestens zwei füllgrössen. Expired - Fee Related DE68924896T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US17659688A 1988-04-01 1988-04-01
PCT/US1989/001314 WO1989009444A1 (en) 1988-04-01 1989-03-30 Cache with at least two fill sizes

Publications (2)

Publication Number Publication Date
DE68924896D1 true DE68924896D1 (de) 1996-01-04
DE68924896T2 DE68924896T2 (de) 1996-07-25

Family

ID=22645015

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68924896T Expired - Fee Related DE68924896T2 (de) 1988-04-01 1989-03-30 Cachespeicher mit mindestens zwei füllgrössen.

Country Status (6)

Country Link
EP (1) EP0359815B1 (de)
JP (1) JP2700148B2 (de)
KR (1) KR930002786B1 (de)
CA (1) CA1314107C (de)
DE (1) DE68924896T2 (de)
WO (1) WO1989009444A1 (de)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1182562B1 (de) * 2000-08-21 2011-05-11 Texas Instruments France Intelligenter Cache-Speicher mit unterbrechbarer Blockvorausholung
US7162588B2 (en) 2002-08-23 2007-01-09 Koninklijke Philips Electronics N.V. Processor prefetch to match memory bus protocol characteristics

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4392200A (en) * 1980-01-28 1983-07-05 Digital Equipment Corporation Cached multiprocessor system with pipeline timing
US4442488A (en) * 1980-05-05 1984-04-10 Floating Point Systems, Inc. Instruction cache memory system
US4370710A (en) * 1980-08-26 1983-01-25 Control Data Corporation Cache memory organization utilizing miss information holding registers to prevent lockup from cache misses
US4489378A (en) * 1981-06-05 1984-12-18 International Business Machines Corporation Automatic adjustment of the quantity of prefetch data in a disk cache operation

Also Published As

Publication number Publication date
EP0359815A4 (en) 1992-04-01
CA1314107C (en) 1993-03-02
JPH02500552A (ja) 1990-02-22
KR930002786B1 (ko) 1993-04-10
EP0359815A1 (de) 1990-03-28
WO1989009444A1 (en) 1989-10-05
EP0359815B1 (de) 1995-11-22
DE68924896T2 (de) 1996-07-25
JP2700148B2 (ja) 1998-01-19
KR900700959A (ko) 1990-08-17

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee