Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
  • H01L21/52—Mounting semiconductor bodies in containers
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
  • H01L21/67005—Apparatus not specifically provided for elsewhere
  • H01L21/67011—Apparatus for manufacture or treatment
  • H01L21/67132—Apparatus for placing on an insulating substrate, e.g. tape
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
  • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
  • H01L21/561—Batch processing
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
  • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
  • H01L21/568—Temporary substrate used as encapsulation process aid
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
  • H01L21/67005—Apparatus not specifically provided for elsewhere
  • H01L21/67011—Apparatus for manufacture or treatment
  • H01L21/67121—Apparatus for making assemblies not otherwise provided for, e.g. package constructions
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/12—Mountings, e.g. non-detachable insulating substrates
  • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
  • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
  • H01L21/6838—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping with gripping and holding devices using a vacuum; Bernoulli devices
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/12—Mountings, e.g. non-detachable insulating substrates
  • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
  • H01L23/15—Ceramic or glass substrates
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
  • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
  • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
  • H01L24/93—Batch processes
  • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
  • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting

Definitions

• the invention relates to an assembly method for an integrated semiconductor wafer device, in particular an integrated semiconductor component arrangement, as a manufacturing intermediate product and an assembly device for carrying out this assembly method.
• active circuits such as logic, memories, processor circuits, and the like are at least partially fabricated on separate substrates and then physically and electrically bonded together to form a functional device.
• Such bonding processes employ sophisticated techniques and improvements are desired.
• a combination of two complementary assemblies, such as CPU and cache on a semiconductor wafer, can be described with the term “on-die”: the CPU has the cache “on-die”, i.e. directly on the same semiconductor wafer , which significantly speeds up data exchange
• ABT assembly and connection technology
• integrated circuits are usually produced on a single semiconductor wafer and individual semiconductor wafers on the wafer are singulated by sawing the integrated circuits along a tear line.
• the individual semiconductor wafers are usually encapsulated separately, for example in multi-semiconductor wafer modules or in other types of housings (packaging).
• a wafer level package (WLP) structure is used as a packaging structure for semiconductor components of electrical products.
• I / O input-output
• ICs integrated circuits
• An electrical redistribution structure is used that includes one or more electrical redistribution layers (RDL).
• RDL can be designed as a structured metallization layer and serves as an electrical interconnection, which is designed to connect the electronic component embedded in the encapsulation with the external connections of the semiconductor component package and / or one or more electrodes of the underside of the semiconductor component package arranged to connect semiconductor wafers.
• DE 102007022 959 A1 shows a semiconductor package in which a semiconductor wafer is embedded in a potting compound.
• a redistribution wiring layer is provided with solder balls for surface mounting of the semiconductor wafer package.
• Vias through the semiconductor package are provided with solder material on a surface of the semiconductor package, with which a second semiconductor package can be stacked on the first.
• US Pat. No. 6,716,670 B1 shows a semiconductor wafer package for surface mounting. Contacts to which a second semiconductor wafer package can be attached are provided on a main surface.
• DE 102006033 175 A1 shows an electronics module that comprises a logic part and a power part. The logic part and the power part are arranged on substrates arranged one above the other and cast together.
• US 2014/0091473 A1 and US 2015/0069623 A1 describe the 3D semiconductor wafer integration of TSMC, with semiconductor wafers being cast in plastic resin and through-plating as through-silicon vias or as metal webs in the potting compound are embedded.
• WO 1998/037580 A1 deals with the underfilling of CSPs and discloses a holder with a recess with side walls for receiving a semiconductor chip with its carrier as an intermediate production product therein.
• US 4953283 A shows a holder for processing chips which is at least partially lined with an elastic means made of metal or resin with a recess for receiving the chips.
• US 2015/0303174 A1 relates to the complex 3D integration and US 2017/0207204 A1 to “integrated fan out packaging”.
• the introduction of the potting compound can lead to a relative displacement of the semiconductor wafers among one another and with respect to a predetermined target position of the semiconductor wafer.
• the shrinkage of the casting compound due to solidification leads to stresses that can lead to uneven deformation.
• a method according to the preamble of claim 1 in which a substrate made of glass with at least one recess formed by corresponding walls for receiving prior to the introduction of casting compound is positioned or fixed by one or more semiconductor wafers relative to the semiconductor wafers in such a way that at least individual semiconductor wafers are surrounded, in particular separated from one another, by the walls of the glass substrate.
• the glass substrate limits the displacement of the semiconductor wafers parallel to the main plane of extent of the substrate or the plastic substrate carrying the semiconductor wafers to less than 100 ⁇ m and, depending on the design, to less than 10 ⁇ m.
• the glass substrate forms a mask with the recesses adapted to the semiconductor wafers, which can preferably already be equipped with through holes (Through Glass Via: TGV) and enable through-hole plating.
• the invention provides a corresponding assembly method for such an integrated semiconductor wafer device as a manufacturing intermediate product according to the characterizing part of claim 1, as well as a corresponding assembly device for carrying out the corresponding method according to claim 8.
• the assembly method according to the invention comprises the following steps:
• a spring manipulator substrate with a manipulation element adapted to the contour space of the semiconductor wafer to be positioned and / or the at least one spring element, relative displacement of the glass substrate to the spring manipulator substrate in such a way that its manipulation element is pretensioned and the spring element is deflected out of the contour space of the semiconductor Wavers moves into the recess,
• LIDE Laser Induced Deep Etching
• the manipulation element can move into the recess of the glass substrate to a maximum depth of less than half the thickness of the glass substrate. This represents a favorable compromise between the necessary manipulation path for the spring element or elements and the smallest possible trimming of the available depth of the recess for receiving the semiconductor wafer.
• the manipulation element preferably moves into the recess of the glass substrate from below, so that the semiconductor wafer can advantageously be fitted into the recess from above.
• a favorable shape for the manipulation element is a cross-section trapezoidal, pedestal-like projection with lateral manipulation flanks for the respective Spring element.
• This projection can preferably be formed in one piece on a plate-shaped base body of the spring manipulator substrate.
• the inclined lateral manipulation flanks result in a gradual and therefore gentle loading of the filigree spring elements, the manipulation elements themselves being designed to be sufficiently stable for a large number of production cycles.
• the semiconductor wafer is preferably placed in the recess in a raised intermediate position on the manipulation element and is lowered into its final position in the recess when the manipulation element is moved out of the recess. There it is held and aligned by the latter in the recess by the extension of the spring manipulator substrate and the associated activation of the spring elements.
• the semiconductor wafer can be subjected to negative pressure in a procedural development.
• a negative pressure application between the glass substrate and the spring manipulator substrate can ensure a relative displacement of these two components.
• suction channels that are continuous in the thickness direction are applied in the spring manipulator substrate, in particular its base body and / or in the manipulation element.
• Fig. 1 is a vertical sectional view of a glass substrate with recesses and
• FIG. 2 shows a horizontal sectional view of a glass substrate with recesses and plated-through holes in an embodiment that is likewise not according to the invention
• 3 shows a vertical sectional illustration of an integrated semiconductor wafer package
• 4 shows a schematic, sectional top view of an embodiment of an integrated semiconductor wafer device with spring elements for aligning the semiconductor wafer
• 5 and 6 are schematic, partial plan views of a glass substrate in a further embodiment with spring elements in two different mounting positions
• FIG. 8 shows an illustration analogous to FIG. 7 with the spring manipulator substrate moved into the glass substrate
• a glass substrate 1 of thickness D is provided with a plurality of recesses 2 and a spacing b.
• through holes 4 - so-called “Through Glass Vias”, abbreviated to TGV - are created, in which a metallization 5 is introduced in the usual way.
• the glass substrate 1 consists at least essentially of an alkali-free glass, in particular an aluminoborosilicate glass or borosilicate glass.
• FIG. 2 shows the top view of a similar glass substrate 1, which in turn has rectangular recesses 2 in top view.
• flanking through holes 4 are made on both sides of the recess 2 shown on the left in FIG. 2 at a distance from its narrow sides 6, 7. Further such through holes 4 are located in two parallel rows below the recess 2 shown on the right in FIG. 2.
• the recesses 2 can - as shown in Figure 1 - be designed as through openings, but also as blind holes.
• its material thickness D can, for example, ⁇ 500 ⁇ m, preferred wise ⁇ 300 pm or even more preferably ⁇ 100 pm.
• the wall thickness b of the walls 3 is ⁇ 500 pm, preferred gradations are ⁇ 300 pm, ⁇ 200 pm, ⁇ 100 pm or ⁇ 50 pm and is preferably less than the material thickness D of the glass substrate 1.
• the ratio b / D the maximum remaining wall thickness b between two recesses 2 in the glass substrate 1 for its material thickness D ⁇ 1: 1, preferably ⁇ 2: 3, ⁇ 1: 3 or ⁇ 1: 6.
• the size of the recesses 2 in the glass substrate 1 is basically chosen so that semiconductor components 9 can be accommodated therein with the smallest possible distance from the side wall surfaces 8.
• the positions of the recesses 2 are selected so that they correspond to the desired subsequent positioning of the semiconductor components 9 implemented as semiconductor wafers in an integrated semiconductor component arrangement - a so-called “chip package” or “fan out package”.
• FIG. 3 now shows schematically how a glass substrate 1 can be used in the production of a chip package.
• the distance between the side wall surfaces 8 of the walls 3 and the opposite sides of the semiconductor components 9 is approximately ⁇ 30 pm, preferably ⁇ 20 pm, ⁇ 10 pm or ⁇ 5 pm.
• a potting compound 12 is poured into the recesses 2 in order to fix the semiconductor components 9 in their position within the glass substrate 1. This provides a compact unit of the glass substrate 1, through holes 4 with metallization 5 made therein and semiconductor components 9 embedded in the potting compound 12.
• recesses 17 for the corners of the components 9 can - as shown in FIG. 4 - in the corner areas of the respective recess 2 be created in the glass substrate 1.
• stops 18 protruding from the side wall surface 8 are arranged on the glass substrate 1, as a result of which so-called “overdeterminations” when fixing the position of the semiconductor component 9 in the recess 2 are avoided.
• the pre-fixing of the semiconductor component 9 is additionally optimized by two spring elements 19 in the side wall surfaces 8 of the glass substrate 1 opposite the stops 18.
• the construction elements recess 17, stop 18 and spring element 19 can also be used separately, each individually or in different combinations in different recesses 2 of an integrated semiconductor wafer device.
• FIGS. 5 and 6 again show, analogously to FIG. 4, a glass substrate 1 with a recess 2 for receiving a semiconductor wafer (not shown here).
• the latter is only indicated by its contour space K, marked with dashed lines in FIGS. 5 and 6, which represents the outer contour assumed by the semiconductor wafer in relation to its top view.
• two spring elements 19 are each formed by spring arms 20 connected at one end to the glass substrate, with their other end directed towards one another, which protrude slightly obliquely into recess 2 in their relaxed position shown in FIG.
• the spring arms 20 engage in the contour space K.
• Fig. 6 the deflected, tensioned position of the spring arms 20 is shown, in which the latter are disengaged from the contour space K and no longer overlap with this.
• FIGS. 7 and 8 the core of which is the spring manipulator substrate 22.
• the latter is produced analogously to the glass substrate 1 with a corresponding filigree process and has a plate-shaped base body 23 and manipulation elements 25 molded on its top 24 in the form of trapezoidal, pedestal-like projections with lateral manipulation flanks 26.
• the outline and the height of these manipulation elements 25 are chosen so that they can cooperate with the spring arms 20 of the spring elements 19 in a suitable manner.
• the spring manipulator substrate 22 is then lowered again, as a result of which, on the one hand, the respective semiconductor component 9 is lowered further into the recess 2 and, on the other hand, the spring arms 20 are released.
• the latter thus act on the semiconductor components 9 and align them precisely in the recess 2.
• the potting of the semiconductor components 9 in the recesses 2 and the application of a rewiring layer and solder balls can then be performed again - as described above and analogously to the prior art.
• suction channels 27, 28 extending in the thickness direction DR in the area of the manipulation elements 25 and between them.
• the suction channels 27 shown in the middle in FIGS. 9a-9d are aligned with the walls 3 between the recesses 2 and, by applying negative pressure p, serve to drive movement during the relative displacement of glass substrate 1 and spring manipulator substrate 22. Via the other suction channels 28, negative pressure is also applied p the semiconductor components 9 are fixed in their position on the manipulation elements 25.
• the deflection of the spring arms 20 is in the order of magnitude of 5-100 ⁇ m.
• the height h of the manipulation elements 25 and thus its maximum penetration depth t into the recess is significantly less, preferably less than half the thickness D of the glass substrate 1.

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• Engineering & Computer Science (AREA)
• Computer Hardware Design (AREA)
• Power Engineering (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Physics & Mathematics (AREA)
• General Physics & Mathematics (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• Manufacturing & Machinery (AREA)
• Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
• Wire Bonding (AREA)
• Chemical & Material Sciences (AREA)
• Ceramic Engineering (AREA)
• Die Bonding (AREA)
• Micromachines (AREA)

Applications Claiming Priority (2)

Publications (1)

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ID=74184654

Family Applications (1)

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Family Cites Families (21)

• 2020
  • 2020-01-23 DE DE102020200817.5A patent/DE102020200817B3/de active Active
• 2021
  • 2021-01-12 EP EP21700424.1A patent/EP4094285A1/de active Pending
  • 2021-01-12 KR KR1020227025570A patent/KR20220127838A/ko unknown
  • 2021-01-12 JP JP2022543701A patent/JP7438374B2/ja active Active
  • 2021-01-12 WO PCT/EP2021/050495 patent/WO2021148281A1/de unknown
  • 2021-01-12 US US17/759,319 patent/US20230096742A1/en active Pending
  • 2021-01-12 CN CN202180010723.8A patent/CN115004346A/zh active Pending
  • 2021-01-15 TW TW110101696A patent/TWI803805B/zh active

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