EP3707972A1 - Procédé et dispositif pour l'intégration de pastilles semi-conductrices - Google Patents

Procédé et dispositif pour l'intégration de pastilles semi-conductrices

Info

Publication number
EP3707972A1
EP3707972A1 EP18792891.6A EP18792891A EP3707972A1 EP 3707972 A1 EP3707972 A1 EP 3707972A1 EP 18792891 A EP18792891 A EP 18792891A EP 3707972 A1 EP3707972 A1 EP 3707972A1
Authority
EP
European Patent Office
Prior art keywords
semiconductor
glass substrate
recesses
semiconductor wafer
side wall
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP18792891.6A
Other languages
German (de)
English (en)
Inventor
Roman Ostholt
Norbert AMBROSIUS
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
LPKF Laser and Electronics SE
Original Assignee
LPKF Laser and Electronics AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by LPKF Laser and Electronics AG filed Critical LPKF Laser and Electronics AG
Publication of EP3707972A1 publication Critical patent/EP3707972A1/fr
Pending legal-status Critical Current

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    • H—ELECTRICITY
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    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
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    • H01L23/5386—Geometry or layout of the interconnection structure
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    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
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    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
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Definitions

  • the invention relates to a method for integrating semiconductor wafers in a small space, in particular 3D integration, in which the semiconductor wafers after positioning relative to a substrate and / or a redistribution layer (RDL) protected by introducing a potting compound and in be fixed in their relative position. Furthermore, the invention relates to a device for use in the method, a corresponding integrated semiconductor wafer device as a production intermediate and as an end product.
  • RDL redistribution layer
  • active circuits such as logic, memory, processor circuits, and the like are at least partially fabricated on separate substrates and then physically and electrically bonded together to form a functional device.
  • Such bonding processes employ sophisticated techniques and improvements are desired.
  • the assembly and connection technology (AVT) deals with the further processing of the semiconductor wafer packaging and integration into the circuitry environment.
  • a wafer level package (WLP) structure is used as a package structure for
  • an electrical rewiring structure which comprises one or more electrical redistribution layers (redistribution layers: RDL).
  • RDL redistribution layers
  • Each RDL can be designed as a structured metallization layer and serves as an electrical
  • An interconnect configured to package the electronic component embedded in the packaging with the external terminals of the semiconductor device package and / or one or more electrodes on the underside of the semiconductor device package
  • Semiconductor device package arranged to connect semiconductor wafers.
  • A1 shows a semiconductor package in which a semiconductor wafer is embedded in a potting compound.
  • a redistribution layer is provided with solder balls for surface mounting the semiconductor wafer package.
  • Through-holes through the semiconductor package are provided with solder material on a surface of the semiconductor package with which a second semiconductor package can be stacked on top of the first.
  • US 6 716 670 B1 shows a surface mount semiconductor wafer package. On a main surface, contacts are provided to which a second semiconductor wafer package can be attached.
  • DE 10 2006 033 175 A1 shows an electronic module comprising a logic part and a power part. Logic part and power unit are arranged on superposed substrates and potted together.
  • US 2015/0303174 A1 relates to the complex 3D integration and US 2017/0207204 A1 to the "integrated fan out packaging".
  • the introduction of the potting compound can lead to a relative displacement of the semiconductor wafer with each other and with respect to a predetermined desired position of the semiconductor wafer. In addition, it comes due to the solidification-related shrinkage of
  • the invention has for its object to provide a way to avoid the associated adverse effects.
  • a method is provided in which prior to the introduction of potting compound a substrate made of glass with a plurality of by wall surfaces or better expressed "partitions" separate recesses for receiving one or more semiconductor wafers positioned relative to the semiconductor wafers such or In this way, one or more semiconductor wafers are arranged in a respective recess and separated from other semiconductor wafers
  • Glass substrate a mask with the recesses adapted to the semiconductor wafer, which may be preferably already equipped with through-holes (through glass via: TGV) and allow a via.
  • TGV through glass via
  • the laser-induced deep etching is used, which has become known under the name LIDE (Laser Induced Deep Etching).
  • LIDE Laser Induced Deep Etching
  • TGV through glass via
  • Redistribution Layer is connected to this layer, wherein the intermediate walls between the recesses enclose the semiconductor wafer on all sides.
  • RDL Redistribution Layer
  • the semiconductor wafers are cast within the recesses of the glass substrate.
  • the semiconductor wafers can be fitted in the glass substrate, so that the substrate could possibly be omitted.
  • the object according to the invention is additionally achieved in that the glass substrate is provided with a plurality of recesses, which are also referred to as cavities, which enclose the semiconductor wafers with a small gap or even fitting, wherein the recesses are delimited by side wall surfaces, have a largely flat course, in particular so no reduced between the surfaces of the glass substrate clear width or no convex extending into the recess wall surface area.
  • a plurality of recesses which are also referred to as cavities, which enclose the semiconductor wafers with a small gap or even fitting, wherein the recesses are delimited by side wall surfaces, have a largely flat course, in particular so no reduced between the surfaces of the glass substrate clear width or no convex extending into the recess wall surface area.
  • the wall surface may have a V-shaped course, that is to say a continuously increasing clear width of the recess, the pitch preferably being constant without
  • a transparent, translucent or transmissive potting compound for example a polymer
  • Redistribution layer and thereon contact elements are applied.
  • Semiconductor wafer device in particular integrated semiconductor device arrangement, as a production intermediate, preferably produced by the method according to the invention, characterized by the following features:
  • a finished semiconductor product device that can be produced from this is an integrated semiconductor wafer device in which removal of the carrier substrate and the adhesive film leaves a glass substrate with recesses formed between intermediate walls, in each of which one or more semiconductor wafers, in particular semiconductor components embedded with a potting compound. Furthermore, the device has a rewiring layer in electrical contact with the one or more semiconductor wafers, in particular semiconductor components and contact elements, in particular solder balls, on the rewiring layer.
  • Fig. 1 is a vertical sectional view of a glass substrate with recesses and
  • FIG. 2 is a horizontal sectional view of a glass substrate with recesses and plated-through holes in a second embodiment
  • Fig. 3 is a vertical sectional view of a glass substrate with recesses and
  • FIG. 5 (a-d) vertical sectional views of various embodiments of a
  • Fig. 6 (a-c) are schematic vertical sectional views of various others
  • Fig. 7 - 9 are schematic, partial plan views of various others
  • Embodiments of a semiconductor integrated wafer device Embodiments of a semiconductor integrated wafer device.
  • a glass substrate 1 of thickness D is provided with a plurality of recesses 2 and a distance b.
  • Through holes 4 - so-called “through glass vias” (abbreviated to TGV) - are placed in the intermediate walls 3 of the glass substrate 1 surrounding the recesses 2, in which a metallization 5 is introduced in a conventional manner.
  • the glass substrate 1 consists at least essentially of an alkali-free glass , in particular an aluminoborosilicate glass or borosilicate glass.
  • FIG. 2 shows the plan view of a similar glass substrate 1, which in turn has rectangular recesses 2 in plan view.
  • the narrow sides 6, 7 flanking through-holes 4 are introduced.
  • Through holes 4 are located in two rows parallel below the recess 2 shown on the right in FIG.
  • the recesses 2 can - as shown in Figure 1 - be formed as a continuous openings, but also as blind holes.
  • Recesses 2 introduced with intermediate walls 3 between them.
  • the opposite side wall surfaces 8 of the recesses 2 are not arranged - as in the embodiment of FIG. 1 - perpendicular to the main plane of the glass substrate 1, but open in a V-shape with respect to FIG. 3, in which the
  • Side wall surfaces 8 occupy a flank angle a relative to the surface normal to the glass substrate 1, which may be up to 10 °, in particular up to 8 ° or 5 °.
  • the side surfaces 8 need not necessarily be flat, they can also be a
  • its material thickness D can be, for example, ⁇ 500 ⁇ m
  • the wall thickness b of the intermediate walls 3 is ⁇ 500 ⁇ m, preferred gradations are ⁇ 300 ⁇ m, ⁇ 200 ⁇ m, ⁇ 100 ⁇ m or ⁇ 50 ⁇ m and is preferably less than the material thickness D of the glass substrate 1. Accordingly, the ratio b / D of the maximum remaining wall thickness b between two recesses 2 in the glass substrate 1 to its material thickness D ⁇ 1: 1, preferably ⁇ 2: 3, ⁇ 1: 3 or ⁇ 1: 6 be.
  • the size of the recesses 2 in the glass substrate 1 is basically chosen so that semiconductor components 9 can be accommodated therein with the smallest possible distance to the side wall surfaces 8.
  • the positions of the recesses 2 are chosen so that they correspond to the desired later positioning of the semiconductor components 9 in an integrated semiconductor component arrangement - a so-called "chip package” or "fan out package”.
  • Fig. 4 a) to f) shows schematically how an inventive glass substrate 1 can be used in the manufacture of a chip package.
  • Fig. 4 a) shows as
  • step d) a potting compound 12 is poured into the recesses 2 in step c) in order to fix the semiconductor components 9 in their position within the glass substrate 1.
  • step d) the adhesive film 1 1 is detached with the carrier substrate 10. This is a compact unit of the glass substrate 1, introduced therein through holes 4 with metallization 5 and embedded in the potting compound 12 semiconductor devices 9 before.
  • a redistribution layer - a so-called “RDL” - 13 is deposited on the side of the unit on which the electronic components 9 are exposed - in Figure 4 e) this is the top after the unit has been turned are, as can be seen in Figure 4 f), applied at corresponding connection points (not shown) of the redistribution layer 13 solder balls 14 for contacting the semiconductor devices.
  • FIG. 5 shows various embodiments of a semiconductor integrated-device arrangement, each of which has been processed up to step c) in FIG. 4.
  • adhesive film 1 1 and a glass substrate 1 with one or more semiconductor devices 9 is implemented fixed in corresponding recesses 2 by means of the potting compound 12.
  • Fig. 5 a) shows a glass substrate 1 with a single semiconductor device 9, Fig. 5 b) with several components 9.
  • Fig. 5 c) are in
  • Edge region to the recesses 2 through holes 4 have been generated, which are partially filled with a metallization 5.
  • FIG. 5 d shows the use of a transparent encapsulant 12, which enables optical data communication 15 between the semiconductor components 9 through the transmissive glass substrate 1.
  • the recess 2 in the glass substrate 1 is cut so closely that the semiconductor component 9 is virtually prefixed in direct contact with the intermediate wall 3 on the carrier substrate 10 in its position in this plane.
  • FIG. 6b takes up the configuration shown in FIG. 3, in which the side wall surfaces 8 of the glass substrate are inclined at a flank angle.
  • the open bottom surface of the recess 2 is in turn dimensioned so that the semiconductor device 9 rests with its foot on the lower edge of the inclined side wall surface 8 and thus also takes place a position pre-fixing of the device.
  • the same effect is achieved in the embodiment shown in Figure 6c, characterized in that two opposite side wall surfaces 8 are provided approximately at half the height respectively with V-shaped projections 16 on which the semiconductor devices 9 is applied.
  • recesses 17 for the corners of the recesses can be made in the corner regions of the respective recess 2 Components 9 may be created in the glass substrate 1.
  • outstanding stops 18 are additionally arranged on the glass substrate 1 by the side wall surface 8, whereby so-called “overdeterminations” in the position fixing of the semiconductor component 9 in the recess 2 are avoided.
  • the prefixing of the semiconductor component 9 is finally additionally optimized by two spring elements 19 in the side wall surfaces 8 opposite the stops 18, the glass substrate 1 being further optimized. It should be noted, however, that the construction elements recess 17, stop 18 and spring element 19 can also be used separately, individually or in different combinations in different recesses 2 of an integrated semiconductor wafer device.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Wire Bonding (AREA)

Abstract

Procédé pour l'intégration de composants semi-conducteurs (9) dans un espace étroit, en particulier pour l'intégration 3D, dans lequel les composants semi-conducteurs (9) sont, après leur positionnement par rapport à un substrat de support (10) et/ou une couche de recâblage (Redistribution Layer RDL) (13), protégés et fixés dans leur position relative par l'introduction d'une masse de scellement (12), caractérisé en ce qu'avant l'introduction de la masse de scellement (12), un substrat de verre (1) comprenant une pluralité de cavités (2) séparées par des parois intermédiaires (3), pour la réception d'un composant semi-conducteur (9) est positionné de telle manière que le composant semi-conducteur (9) est entouré par les surface de parois latérales (8) lui faisant face des parois intermédiaires (3) respectives du substrat de verre (1).
EP18792891.6A 2017-11-10 2018-10-17 Procédé et dispositif pour l'intégration de pastilles semi-conductrices Pending EP3707972A1 (fr)

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DE102017126410 2017-11-10
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PCT/EP2018/078361 WO2019091728A1 (fr) 2017-11-10 2018-10-17 Procédé et dispositif pour l'intégration de pastilles semi-conductrices

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CN (1) CN111434191B (fr)
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CN111434191A (zh) 2020-07-17
US11515259B2 (en) 2022-11-29
MY197514A (en) 2023-06-19
US20200266152A1 (en) 2020-08-20
KR20200086319A (ko) 2020-07-16
JP7090153B2 (ja) 2022-06-23
CN111434191B (zh) 2023-10-20
WO2019091728A1 (fr) 2019-05-16
KR102538306B1 (ko) 2023-06-07

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