JP7090153B2 - 半導体ウェハの集積方法及び装置 - Google Patents
半導体ウェハの集積方法及び装置 Download PDFInfo
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Description
-接着層を介して固定された少なくとも1つの半導体ウェハ、特に半導体部品を有するキャリア基板を供給する工程、
-少なくとも1つの切り欠きを有するガラス基板を供給する工程、
-少なくとも1つの半導体ウェハ、特に半導体部品が少なくとも1つの切り欠き内に配置されるように、ガラス基板をキャリア基板の接着層上に位置決めする工程、
-注封材料を用いて、少なくとも1つの半導体ウェハ、特に半導体部品を少なくとも1つの切り欠きに埋め込む工程、及び、
-半導体ウェハ、ガラス基板、及び注封材料を含む残りのパッケージから、キャリア基板及び接着フィルムを取り除く工程によって特徴付けられる。
-キャリア基板、
-その上に配置された接着フィルム、
-その接着フィルム上に固定された少なくとも1つの半導体ウェハ、特に半導体部品、及び、
-接着フィルムに固定され、間に隔壁を形成する複数の切り欠きを有するガラス基板であって、各切り欠きには、1つ以上の半導体ウェハ、特に半導体部品が注封材料で埋め込まれているガラス基板、によって特徴付けられる。
2 切り欠き
3 隔壁
4 貫通穴
5 メタライゼーション
6、7 側面
8 側壁面
9 半導体部品
10 キャリア基板
11 接着フィルム
12 注封材料
13 再配線層
14 はんだボール
15 光データ通信
16 V字形突起
17 凹部
18 止め部
19 ばね要素
D 材料厚
F 表面法線
a フランク角
b 壁厚
Claims (23)
- 3D集積のために、限定された空間に半導体部品(9)を集積する方法であって、
キャリア基板(10)及び/又は再配線層(RDL)(13)に対して位置決めした後、注封材料(12)を導入することにより、少なくとも1つの半導体部品(9)を、それらの相対位置で保護及び固定する集積方法において、
前記注封材料(12)を導入する前に、隔壁(3)で分離された多数の切り欠き(2)を有し、それぞれ少なくとも1つの半導体部品(9)を受け入れる役割を果たすガラス基板(1)は、前記少なくとも1つの半導体部品(9)が、前記ガラス基板(1)のそれぞれの前記隔壁(3)の、前記半導体部品(9)に面する側壁面(8)によって囲まれるように配置され、
レーザー誘起ディープエッチングにより、前記隔壁(3)は壁厚(b)が100μm未満で製造されていることを特徴とする集積方法。 - 前記複数の切り欠き(2)は、貫通穴又は止まり穴として具体化されることを特徴とする請求項1に記載の方法。
- 前記ガラス基板(1)に貫通穴(4)が導入され、少なくとも個々の前記貫通穴には、前記複数の切り欠き(2)内に前記半導体部品(9)を相対位置で固定する前に、スルーメッキのためのメタライゼーション(5)が施されていることを特徴とする請求項1又は2に記載の方法。
- 前記半導体部品(9)は、前記注封材料(12)を導入する前に、それぞれの前記切り欠き(2)に固定されていることを特徴とする請求項1乃至3のいずれか一項に記載の方法。
- 前記半導体部品(9)は、少なくとも1つの側壁面(8)との接触により固定されることを特徴とする請求項4に記載の方法。
- それぞれの前記側壁面(8)において、1つ以上の突起(16)及び/又はばね要素(19)が、前記半導体部品(9)を固定するために使用されることを特徴とする請求項5に記載の方法。
- 複数の凹部(17)が、前記ガラス基板(1)の前記切り欠き(2)の角領域に導入されることを特徴とする請求項1乃至6のいずれか一項に記載の方法。
- 透明又は透過性のポリマーが、前記注封材料(12)として使用されることを特徴とする請求項1乃至7のいずれか一項に記載の方法。
- ファンアウトパッケージを製造するための、3D集積で限定された空間に半導体部品を集積する方法において、
-接着層(11)を介して固定された少なくとも1つの半導体部品(9)を有するキャリア基板(10)を用意する工程と、
-少なくとも1つの切り欠き(2)を有するガラス基板(1)を用意する工程と、
-前記少なくとも1つの半導体部品(9)が、前記少なくとも1つの切り欠き(2)内に配置されるように、前記ガラス基板(1)を前記キャリア基板(10)の前記接着層(11)に位置決めする工程と、
-注封材料(12)を用いて、前記少なくとも1つの半導体部品(9)を前記少なくとも1つの切り欠き(2)に埋め込む工程と、
-キャリア基板(10)及び接着フィルム(11)を、半導体部品(9)、ガラス基板(1)、及び注封材料(12)を含む残りのパッケージから取り除く工程と、
を備えることを特徴とする方法。 - 再配線層(13)及びその上の接触要素は、前記少なくとも1つの半導体ウェハと電気的に接触した状態で前記パッケージに設けられることを特徴とする請求項9に記載の方法。
- 製造中間製品としての集積半導体部品装置において、
-キャリア基板(10)と、
-その上に配置された接着フィルム(11)と、
-前記接着フィルム(11)上に固定された少なくとも1つの半導体ウェハと、
-前記接着フィルム(11)に固定され、間に隔壁(3)を形成する複数の切り欠き(2)を有するガラス基板(1)であって、各々の前記切り欠き(2)に1つ以上の半導体ウェハが注封材料(12)で埋め込まれているガラス基板(1)と、を備え、
レーザー誘起ディープエッチングにより、前記隔壁(3)は、100μm未満の壁厚(b)を有することを特徴とする集積半導体部品装置。 - ファンアウトパッケージ形態の最終製品としての集積半導体部品装置において、
-間に隔壁(3)を形成する複数の切り欠き(2)を有し、各々の前記切り欠き(2)に1つ以上の半導体ウェハが注封材料(12)で埋め込まれているガラス基板(1)と、
-前記1つ以上の半導体ウェハと電気的に接触している再配線層(13)と、
-前記再配線層(13)上の接触要素と、を備え、
レーザー誘起ディープエッチングにより、前記隔壁(3)は、100μm未満の壁厚(b)を有することを特徴とする集積半導体部品装置。 - 前記隔壁(3)の壁厚(b)は、50μm未満であることを特徴とする請求項11又は12に記載の装置。
- 前記隔壁(3)の壁厚(b)は、前記ガラス基板(1)の材料厚(D)よりも小さいことを特徴とする請求項11乃至13のいずれか一項に記載の装置。
- 前記ガラス基板(1)の2つの切り欠き(2)間の前記隔壁(3)の最大残存壁厚(b)と前記基板の材料厚(D)の比率(b/D)が、1:1未満であることを特徴とする請求項11に記載の装置。
- 隔壁(3)の側壁面(8)と、半導体ウェハとの間の距離は、30μm未満であることを特徴とする請求項11乃至15のいずれか一項に記載の装置。
- 側壁面(8)の突起(16)の領域において、
隔壁(3)の側壁面(8)と、半導体ウェハとの間の距離は、ゼロであることを特徴とする請求項11乃至15のいずれか一項に記載の装置。 - 前記切り欠き(2)間の前記隔壁(3)の側壁面(8)は、前記ガラス基板(1)の表面法線(F)に対して0°から10°の間のフランク角(a)を有することを特徴とする請求項11乃至17のいずれか一項に記載の装置。
- 前記隔壁(3)の2つの対向する側壁面(8)は、前記半導体ウェハをそれぞれの前記切り欠き(2)に固定する突起(16)を形成するために、V字形及び/又は砂時計形のコースを形成することを特徴とする請求項11乃至18のいずれか一項に記載の装置。
- 前記ガラス基板(1)は、少なくとも実質的に無アルカリガラスからなることを特徴とする請求項11乃至19のいずれか一項に記載の装置。
- 前記半導体ウェハを固定するための、1つ以上の止め部(18)、突起(16)及び/又はばね要素(19)が、それぞれの側壁面(8)に配置されることを特徴とする請求項11乃至20のいずれか一項に記載の装置。
- 前記ガラス基板(1)の前記切り欠き(2)の角領域に、複数の凹部(17)が導入されることを特徴とする請求項11乃至21のいずれか一項に記載の装置。
- 前記ガラス基板(1)の材料厚さ(D)が500μm未満であることを特徴とする請求項11乃至22のいずれか一項に記載のガラス基板(1)を備えた装置。
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DE102020112879A1 (de) | 2020-05-12 | 2021-11-18 | Lpkf Laser & Electronics Aktiengesellschaft | Verbundstruktur mit zumindest einer elektronischen Komponente sowie ein Verfahren zur Herstellung einer solchen Verbundstruktur |
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US11515259B2 (en) | 2022-11-29 |
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KR20200086319A (ko) | 2020-07-16 |
US20200266152A1 (en) | 2020-08-20 |
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