EP1481423A2 - Module electronique, tableau muni de modules electroniques a separer et procede de production correspondant - Google Patents

Module electronique, tableau muni de modules electroniques a separer et procede de production correspondant

Info

Publication number
EP1481423A2
EP1481423A2 EP03717135A EP03717135A EP1481423A2 EP 1481423 A2 EP1481423 A2 EP 1481423A2 EP 03717135 A EP03717135 A EP 03717135A EP 03717135 A EP03717135 A EP 03717135A EP 1481423 A2 EP1481423 A2 EP 1481423A2
Authority
EP
European Patent Office
Prior art keywords
component
electronic module
electronic
component layer
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP03717135A
Other languages
German (de)
English (en)
Inventor
Michael Bauer
Wolfram Eurskens
Gerold GRÜNDLER
Rudolf Kerler
Heinz Pape
Peter Strobel
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of EP1481423A2 publication Critical patent/EP1481423A2/fr
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
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    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Definitions

  • the invention relates to an electronic module, a use with electronic modules to be separated and a method for their production.
  • Highly integrated electronic modules can have a number of electronic semiconductor components or semiconductor chips and, if appropriate, passive components. These electronic components of the module can be connected to one another in an electrically conductive manner with the aid of a rewiring plate or foil. However, if the electronic module comprises a large number of electronic components, this requires a relatively large area.
  • the components can also be built up on separate, organic ceramic substrates using multilayer technology for wiring and subsequent covering or covering with a plastic compound in the form of casting resin or molding compound.
  • An object of the invention is to provide compact electronic modules.
  • an electronic module with a plurality of electronic components has vertically staggered component layers with at least one semiconductor component and / or one semiconductor chip and / or one passive component in each component position. These electronic components are connected to one another via areas of first contact bumps and / or bonding wire connections that are exposed within the respective component positions. Bindings and electrically interconnected interconnects arranged between the component layers and connected to the exposed areas.
  • Such an electronic module preferably has at least two vertically staggered component layers, each component layer according to one embodiment of the invention having a plate or disk-shaped contour.
  • any three-dimensional structuring of electronic modules can be achieved which, apart from the enveloping plastic molding compound or the synthetic resin, does not require any support structures.
  • the construction of such modules can be extremely compact compared to a planar rewiring technology, since the rewiring between the components can be designed with a large spatial freedom in terms of design freedom.
  • the component layers each have semiconductor components and / or semiconductor chips and / or passive components embedded in molding compound.
  • synthetic resin can also be used to embed the electronic components.
  • Such a molding compound which is already used in conventional leadframe or BGA housings, not only serves to protect the sensitive electronic components, but at the same time serves as a substrate for rewiring and components of a further layer of electronic components.
  • Each of the component layers thus serves as a printed circuit board body produced by injection molding for the component layer built on it.
  • the electronic module has external contacts on at least one surface.
  • Such external contacts can, for example, as Contact bumps or the like are designed and are used to contact the electronic module with a higher-level circuit carrier, such as a circuit board.
  • the external contacts are typically located on an underside of the housing of the module, but can in principle be arranged on all sides of the housing, for example to enable further three-dimensional stacking of electronic modules.
  • a further embodiment of the invention provides that in each case an upper arch section of a bond wire connection which is exposed within a component layer is in conductive connection with a conductor track of a further component layer.
  • the bond wire connections between the contact areas of the electronic components and contact connection areas on the respective conductor track level are used simultaneously or, if appropriate, exclusively as vertical connections between the top and bottom of this molding substrate, in addition to contacting the electronic components with the wiring layer on which they are built.
  • the bond wire connections thus simultaneously serve as vias.
  • an upper section of a first bump exposed within a component layer is in conductive connection with a conductor track.
  • contact bumps in the form of solder balls or thermocompression heads (so-called stud bumps) can also be used. These thermocompression heads or solder balls thus serve to connect the electronic components of a component layer with the conductor tracks and the electronic components of a subsequent component layer.
  • the vertical electrical connections between component layers by means of contact bumps can have the advantage of greater compactness compared to bond wire connections, since no further support point for the other end of the bond wire is necessary.
  • the electronic modules according to the invention can be produced either individually or in use.
  • the modules are separated from a plate at the end of the production process, for example by sawing.
  • Such a benefit is typically constructed as a larger plate divided into rows and columns, which is separated after it has been processed.
  • strip-like benefits are also possible.
  • a method according to the invention for producing an electronic module comprises the following steps: a) providing a flat carrier strip with a metallic structure applied to a carrier top, b) applying electronic components to the carrier top, c) applying first contact bumps and / or wire bond connections on contact surfaces of the electronic components, d) embedding the electronic components and the first contact bumps or the wire bond connections in a molding compound or in a synthetic resin to produce a first component layer, e) exposing the upper arch sections of the wire bond connections or from upper sections of the first contact bumps, f) applying conductor tracks to an upper part of the component layer of the first component layer, including the exposed upper sections, g) repeating the method steps b) b one or more times is f) for each additional vertically staggered component location to which a further component location or the following method steps b) to d) for an uppermost lying construction part ⁇ location of the electronic module.
  • An alternative method for producing an electronic module with a plurality of electronic components by separating them from a single use provides for the last, additional process step to separate the benefits into electronic modules by sawing or laser cutting.
  • the molding compound of the component layers is applied by means of the transfer molding method.
  • the component layers can also be formed by means of a synthetic resin, which is applied in each case by casting.
  • the upper arc sections of the bond wire connections or the upper sections of the first contact bumps are exposed according to an exemplary embodiment of the method by means of laser ablation.
  • An alternative method provides that these upper arc sections or upper sections are exposed using an etching process.
  • the conductor tracks of the rewiring layers between the individual component layers are sputtered onto metal over the entire area, followed by photolithographic structuring and galvanic coating. Layering applied with another metal layer.
  • An alternative embodiment of the 'method provides that the printed circuit Brue by mask sputtering of metal and subsequent galvanic coating talllage with a further metal can be applied.
  • Another alternative exemplary embodiment of the method according to the invention provides that the conductor tracks are produced by means of structured application of electrically conductive plastic (nanopaste). This process is also known as dispensing.
  • each component layer can be made more adhesive by mechanical roughening or by plasma etching before the application of a further component layer.
  • the layers of the component layers do not necessarily have to be flat, but may have height gradations that bring additional degrees of freedom in the manufacture of the most compact electronic modules possible.
  • a molding or synthetic resin compound which is already used in conventional leadframe or BGA housings, not only serves to protect the electronic components in the present case, but at the same time serves as a carrier substrate for rewiring and other electronic components of a further layer of components.
  • Each component layer thus serves as a printed circuit board body produced by injection molding or casting. This enables a three-dimensional arrangement of the active and passive electronic components in any number of positions.
  • bonding wire connections except for contacting the construction elements to the respective wiring layer, on which they are constructed, at the same time or possibly exclusively as verti ⁇ kale connections between upper and lower surfaces of the respective gene mold substrates (component location) used.
  • the bond wire connections serve as vias. Studbumps (thermocompression heads) or other contact bumps (e.g. solder balls) can also be used to connect up to another component location.
  • a metal layer e.g. B. copper
  • sputtered and structured and reinforced with conventional methods of micro-wiring as rewiring are galvanically reinforced and etched back. If a metal layer is applied over the entire surface, a structuring is produced by means of a photolithography before or after the galvanic reinforcement with a further metal layer.
  • the production of the electronic modules can either take place in the utility, whereby the modules are separated from a plate at the end of the production process.
  • the electronic modules can also be processed individually.
  • An advantage of the invention is that, on the one hand, an already known, proven, light and inexpensive material is used, which means that a separate and expensive carrier substrate can be saved. This can be achieved by taking over its function through the double function of existing components.
  • a molding compound also serves as a covering. Bond wires also serve as vias. Many of the essential manufacturing steps have already been introduced and qualified.
  • the structure of the electronic modules is three-dimensional, which enables a high integration density or potential for miniaturization.
  • connections can be realized much shorter compared to planar modules, which is particularly advantageous for high-frequency applications.
  • the unbundling of a circuit is also easier if, in addition to the route around a component, it is also possible to route lines above or below the component.
  • the construction technique is essentially layered, with the molding compound serving as the basis for a theoretically unlimited number of rewiring layers. This enables the use of known planar techniques and tools.
  • This layer-like construction technique which consists of largely planar component layers, can be easily deviated from in individual cases, so that the layer thickness in one component layer can be different.
  • platforms or recesses for component assembly can be easily implemented at different heights within a shift. Compared to pure laminar technology, this gives additional degrees of freedom in the three-dimensional design. Adjustment marks are also possible and roughened or structured areas to improve the adhesion between the individual layers.
  • molding compound is that the proportion of plastic in organic substrates is relatively high, which also means increased moisture absorption. In the typically used compression molding compounds with high density, this is not the case, so that a clotting ⁇ ger sensitivity to solder shock resulting therefrom.
  • One aspect of the invention is to use a flat injection-molded module housing as a printed circuit board body with integrated active and passive components of various types.
  • the usual procedure for the production of electronic modules is largely reversed, since the installation positions of components, wiring and plated-through holes are created as far as possible beforehand and a circuit board body subsequently flows around the components and serves as a carrier for the next layer.
  • the component connections (bond wires, stud bumps, etc.) have a spatial structure with which contact can be made with different layers. After components are applied and contacted on an existing substrate, a molding process takes place.
  • connections and the mold cavity are matched to one another in such a way that the connections are exposed after the molding process or are only covered by a few micrometers of the molding material.
  • the parts of the component connections located near the mold surface are exposed and used to connect rewiring (e.g. thin film, screen printing, etc.).
  • the surface of the molding material with this rewiring serves as a substrate for the construction of further components with a subsequent further molding process. This structure can be repeated any number of times.
  • connections can be exposed, for example, by lasering, etching or grinding.
  • the subsequent rewiring on the mold surface can be carried out, for example, using thin film technology (sputtering, photo structuring, galvanic amplification, etching), thick film technology or by dispensing connecting lines (e.g. electrically conductive plastic).
  • the bond wires or stud bumps are used as vias.
  • the method described is suitable for packages in which each individual circuit has its own mold cavity as well as for packages in which several circuits are manufactured with a common mold cavity and the first are separated at the end of assembly.
  • FIG. 1 shows an electronic module according to the invention with three vertically staggered component layers in a schematic cross-sectional illustration.
  • FIG. 2 shows a schematic cross section of a first process step in the production of electronic modules according to the invention in use.
  • FIGS. 3 to 5 show successive process steps for the construction of the electronic modules.
  • FIG. 6 shows a detail of a vertical wiring between two component layers.
  • FIG. 7 shows a perspective oblique view of a section of a rewiring level made of conductor tracks on an upper side of the component layer.
  • FIG. 8 shows a further perspective oblique view of the rewiring level corresponding to FIG. 7 with a semiconductor chip mounted on a chip island.
  • FIGS. 9 and 10 each show, in successive manufacturing steps, a section of a finished processed and freed from a carrier layer.
  • Figure 11 shows a detail of an alternative vertical connection between two adjacent
  • FIG. 1 shows an electronic module 2 according to the invention, which has a plurality of vertically staggered component layers 21, 22, 23 with at least one electronic component 6 in each component position.
  • the electronic components 6 are interconnected within the respective component layers 21, 22, 23 exposed areas 102 of bond wire connections 10 and electrically conductively connected to one another via conductor tracks 83 arranged between the component layers 21, 22, 23 and connected to the exposed areas 102.
  • three vertically staggered component layers 21, 22, 23 are provided, each consisting of a molding compound 141 or a synthetic resin, and in which the electronic components 6 and their bond wire connections 10 are embedded ,
  • a semiconductor chip 65 can be seen, which is applied to a chip brush 85 with a passive rear side 67.
  • the chip island 85 simultaneously forms part of a lower side 142 of the housing, but can optionally also be covered by molding compound 141 or synthetic resin. Bonding wire connections 10 to contact connection areas 84 are from contact areas 68 on the active chip surface 66, which is opposite the passive rear side 67
  • Conductor tracks 83 and out of external contact surfaces 144 In the exemplary embodiment shown, only two bond wire connections 10 are shown, each leading to external contact areas 144, on which external contacts 145 in the form of second bumps 146 are applied. These external contacts 145 or second contact bumps 146 protrude from the underside 142 of the housing and are used in the present case for solder mounting on a printed circuit board or another type of higher-level circuit carrier.
  • the bond wire connections 10 each have an initially approximately vertically upward course from the active chip surface 66, form an upper arc section 101 and are then guided to contact connection areas 84 which are arranged next to the electronic component 6.
  • the dimensions of the first component layer 21 made of molding compound 141 are such that the upper arc sections 101 of the bond wire connections are just embedded in molding compound 141.
  • smaller areas of the bond wire connection 10 are exposed in the area of the upper arch section 101, which results in exposed areas 102 which are arranged in a flat trough, hereinafter referred to as contact trough 26, on the top of the component layer 24 (cf. figures 6 to 8).
  • Conductor tracks 83 each lead from these exposed areas 102 of the upper arch sections 101 of the bond wire connections 10 in any two-dimensional structure.
  • the conductor tracks 83 are each located on the top 24 of the component layer and protrude into a bottom 25 of the component layer of a next second or third component layer 22, 23. In the case of stepped component layers, the conductor tracks 83 run vertically in sections, so that they run in three-dimensional structuring.
  • a further semiconductor chip 65 of smaller dimensions than the first semiconductor chip 65 is mounted in a second component position 22 on a further chip island 85.
  • the right of the other semiconductor chip 65 is a passive component 61 is mounted, which is mounted on contact pins 62 on ent ⁇ speaking contact pads 84 of circuit traces 83rd Further contacting of the passive component 61 in a third component layer 23 applied via the second component layer 22 is unnecessary.
  • the semiconductor chip 65 in the second component layer 22 in turn has bond wire connections 10, which are likewise connected to an upper arc section 101 and an exposed area 102 therein with conductor tracks 83 on the component layer top 24 of the second component layer 22.
  • the component layer top 24 of the second component layer 22 also has conductor tracks 83 in two dimensions Structuring on.
  • a third component layer 23 is applied over the second component layer 22, in which electronic components 6 are in turn embedded.
  • the electronic components 6 of the third component layer 23 are indicated as semiconductor components 63 and also as a further semiconductor chip 65, which in turn are connected via bond wire connections 10 to contact connection areas 84 of conductor tracks 83 on the component layer top 24 of the second component layer 22.
  • the third component layer 23 in the exemplary embodiment shown forms the uppermost component layer and its component layer top 24 simultaneously forms an upper side 143 of the housing, the upper arc sections 101 of the bond wire connections 10 running in this component layer 23 are not guided to the outside. Rather, the upper arc sections 101 of the bond wire connections 10 are covered by a thin layer of molding compound 141, so that a flat and closed component layer top 24 or housing top 143 is formed.
  • the maximum height of the electronic module 2 is only predetermined by mechanical and manufacturing limits.
  • the vertical connections between the different component layers can also be formed via bumps in the form of solder balls (see FIG. 11) or thermocompression heads, so-called stud bumps. These designs can also be used side by side in an electronic module, depending on the manufacturing options.
  • the electronic module according to FIG. 1 can either be produced in the form shown as a single component or can be obtained from a greater benefit by being separated.
  • the Successive process steps in the production by means of processing greater benefits are illustrated in more detail in the following FIGS. 2 to 10.
  • FIG. 2 shows a schematic cross section of a metallic carrier strip 8, on which further metallic structures in the form of conductor tracks 83, contact connection areas 84 or chip islands 85 are applied.
  • the carrier strip 8 forms the supporting structure for building up a first component layer 21 and can be removed in a late process step (cf. FIGS. 9, 10).
  • the carrier strip 8 can either be designed as an elongated carrier, on which several electronic modules are built in a row in a row. However, it can also be designed as a larger disk-shaped carrier on which the electronic modules to be separated later are arranged in rows and columns and are sawn or otherwise separated from one another.
  • FIG. 3 shows a further partial section of the carrier strip 8 with conductor tracks 83 or chip islands 85 applied thereon.
  • a semiconductor chip 65 with a passive rear side 67 is applied to each of the two chip islands 85 shown.
  • An active chip surface 66 of each semiconductor chip 65 lying opposite the passive rear side 67 has contact areas 68 which are each in an electrically conductive connection via bond wire connections 10 with contact connection areas 84 on the conductor tracks 83.
  • the spatial geometric shape of the bond wire connections 10 must be ensured with high precision, since the height of an upper arch section 101 of each bond wire connection 10 must extend straight up to a component layer top side 24 of the respective component layer. In addition, the positioning of the upper arc section 101 for laser ablation or selective etching or grinding must be exactly determined.
  • FIG. 4 shows a further partial section of a panel 4 with a plurality of electronic modules to be separated.
  • a molding compound 141 which surrounds the semiconductor chips 65 and the bond wire connections 10, is applied to a carrier top side 81 of the carrier strip 8.
  • the upper arc sections 101 of the bond wire connections 10 can either protrude minimally from the component layer top side 24 or can be completely covered by the latter.
  • the components can alternatively also be cast in a synthetic resin.
  • FIG. 5 shows, in a partial cross section, the benefit 4, in which the upper arch sections of the bond wire connections are exposed in such a way that they protrude from the top 24 of the component layer 21 of the first component.
  • This upper arc section 101 thus has an exposed area 102, which is arranged in a contact recess 26.
  • FIG. 6 shows this relationship in a detail section in which the contact trough 26 and the exposed area 102 of the upper arch section 101 of the bond wire connection 10 projecting therefrom can be clearly recognized.
  • the contact recess 26 is designed as a flat depression, which can be produced, for example, by a laser ablation process or by punctual etching. Alternatively, the contact recess 26 can also be realized by partially grinding the top 24 of the component layer.
  • FIG. 7 shows an oblique view of the top side of the component layer 24 with conductor tracks 83 applied thereon and with part of a chip island 85.
  • the conductor tracks 83 are used for rewiring from the upper arc sections 101 of the bond wire connections 10 to further contact connection areas 84 on the component layer top side 24.
  • the conductor tracks 83 enable one Freedom of design in the cable routing that would not be possible with conventional vias.
  • Most of the conductor tracks 83 end on one side in a contact depression 26, which they completely fill, an intimate electrically conductive contact being made with the exposed area 102 of each arc section 101.
  • the respective other end of most conductor tracks 83 is designed as a contact connection area 84 for contacting one end of a bond wire connection 10 to an electronic component 6.
  • individual conductor tracks 83 can be provided without connection to electronic components 6. In this case, they are used only for contacting with bond wires.
  • the conductor tracks 83 and the chip islands 85 can be produced either by sputtering a thin surface over the entire surface
  • Metal layer for example aluminum
  • photolithographic structuring of the desired conductor track structures or also by mask sputtering of metal With this so-called thin-film technique, the metallic surface is then further reinforced by a galvanic deposition process. Finally, a thin layer is removed by etching.
  • the conductor tracks 83 and the chip islands 85 can alternatively be produced by thick-film technology or, for example, by applying connecting lines in the form of electrically conductive plastic, so-called nanopastes. This latter procedure is also known as dispensing.
  • FIG. 8 shows a further oblique view in which a semiconductor chip 65 is applied to the chip island 85. Bonding wire connections lead from the contact areas 68 on the active chip surface 66 to the contact connection areas 84 of the conductor tracks 83, whereby an electrically conductive connection is established from the contacts of the semiconductor chip 65 to the contacts of the electronic components located underneath.
  • FIG. 9 shows a finished processed benefit 4 in a partial cross section, from which the individual electronic modules 2 can be obtained by sawing.
  • the benefit 4 has only three component layers 21, 22, 23, but can also have a significantly larger number of component layers, depending on the requirements and the manufacturing possibilities.
  • the electrical connections between the component layers stacked one on top of the other are made via upper arc sections 101 of bond wire connections 10 and associated conductor tracks 83 of an overlying component layer.
  • the electronic components 6 can be arranged in almost any way, which leads to a high degree of flexibility of the electronic modules 2 that can be realized with them.
  • the carrier strip 8 can finally be removed (FIG. 9).
  • this is preferably carried out by etching, as a result of which external contact surfaces 144 on a housing underside 142 of the housing 14 are exposed. These external contact surfaces 144 can then be provided with external contacts 145, for example in the form of second contact bumps 146 as shown in FIG. 10.
  • the panel 4 can finally be divided into individual electronic modules 2 along the saw marks 16. This can be done, for example, by sawing or by laser cutting. Through this separation, electronic modules 2 are obtained, as are shown in FIG. 1 and have already been explained.
  • FIG. 11 shows a further detailed cross section of an alternative configuration of the plated-through holes from one component position to the next.
  • a semiconductor chip 65 - first contact bumps 12 in the form of solder balls 121 are applied.
  • These first contact bumps 12 are also initially completely surrounded by molding compound 141, so that an upper section 123 of the first contact bumps 12 does not protrude from the upper part 24 of the component layer.
  • a contact recess 26 is in turn formed around the contact bump 12 by etching, grinding or laser removal methods, so that an exposed region 102 of the first contact bump 12 is created.
  • the contact recess 26 and the exposed area 102 of the upper section 123 of the contact bump 12 can then be provided with a metallization in the same way as shown in FIG. 8.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Ceramic Capacitors (AREA)

Abstract

L'invention concerne un module électronique muni de composants électroniques, disposés en couches de composants (21, 22, 23) empilées verticalement, qui sont interconnectées de manière électroconductrice, par l'intermédiaire de zones dégagées (102) de points de pic (12) ou de connexions par liaison (10), situées dans chacune des couches de composants, ainsi que par l'intermédiaire de tracés conducteurs (83) disposés entre les couches de composants et communiquant avec les zones dégagées. L'invention concerne en outre un procédé permettant de produire ledit module électronique, soit dans un tableau, soit sous forme de composants individuels.
EP03717135A 2002-03-07 2003-03-06 Module electronique, tableau muni de modules electroniques a separer et procede de production correspondant Withdrawn EP1481423A2 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE10209922 2002-03-07
DE10209922A DE10209922A1 (de) 2002-03-07 2002-03-07 Elektronisches Modul, Nutzen mit zu vereinzelnden elektronischen Modulen und Verfahren zu deren Herstellung
PCT/DE2003/000729 WO2003075347A2 (fr) 2002-03-07 2003-03-06 Module electronique, tableau muni de modules electroniques a separer et procede de production correspondant

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EP1481423A2 true EP1481423A2 (fr) 2004-12-01

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EP (1) EP1481423A2 (fr)
DE (1) DE10209922A1 (fr)
WO (1) WO2003075347A2 (fr)

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US20050052830A1 (en) 2005-03-10
WO2003075347A2 (fr) 2003-09-12
US7276785B2 (en) 2007-10-02
WO2003075347A3 (fr) 2003-12-04
DE10209922A1 (de) 2003-10-02

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