EP3373331A1 - Halbleitergehäuse mit versteifungsring - Google Patents

Halbleitergehäuse mit versteifungsring Download PDF

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Publication number
EP3373331A1
EP3373331A1 EP18154712.6A EP18154712A EP3373331A1 EP 3373331 A1 EP3373331 A1 EP 3373331A1 EP 18154712 A EP18154712 A EP 18154712A EP 3373331 A1 EP3373331 A1 EP 3373331A1
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EP
European Patent Office
Prior art keywords
semiconductor die
semiconductor
interposer
top surface
stiffener ring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP18154712.6A
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English (en)
French (fr)
Other versions
EP3373331B1 (de
Inventor
Tai-Yu Chen
Wen-Sung Hsu
Sheng-Liang Kuo
Chi-Wen Pan
Jen-Chuan Chen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
MediaTek Inc
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MediaTek Inc
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Publication date
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Publication of EP3373331A1 publication Critical patent/EP3373331A1/de
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Publication of EP3373331B1 publication Critical patent/EP3373331B1/de
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Definitions

  • the present invention relates generally to semiconductor packaging and, more particularly, to improvements in dissipation of heat from semiconductor devices in such packages.
  • an IC chip During operation of an integrated circuit (IC), an IC chip generates heat, thus heating the entire electronics package that contains the chip. Because the performance of the IC chip degrades as its temperature increases, and because high thermal stresses degrade the structural integrity of the electronics package, this heat must be dissipated.
  • IC integrated circuit
  • electronic packages use a metal lid to dissipate heat.
  • the heat from the chip is transferred to the metal lid via a thermally conductive chip/lid interface.
  • the heat is then transferred from the lid to the ambient atmosphere via convection or to a heat sink mounted on the lid.
  • a semiconductor package is defined in claim 1 and includes a package substrate having a top surface and a bottom surface, an interposer mounted on the top surface of the package substrate, a first semiconductor die and a second semiconductor die mounted on the interposer in a side-by-side manner, and a stiffener ring secured to the top surface of the package substrate.
  • the stiffener ring encircles the first semiconductor die and the second semiconductor die.
  • the stiffener ring comprises a reinforcement rib striding across the interposer.
  • the heat sink is preferably directly bonded to the rear surface of the first semiconductor die and the rear surface of the second semiconductor die through a thermal interface material (TIM) layer.
  • the reinforcement rib is preferably integrally connected to the stiffener ring through a downset portion.
  • a semiconductor package is defined in claim 8 and includes a package substrate having a top surface and a bottom surface, an interposer mounted on the top surface of the package substrate, a first semiconductor die and a second semiconductor die mounted on the interposer in a side-by-side manner, a molding compound encapsulating the first semiconductor die and the second semiconductor die, and a stiffener ring secured to the top surface of the package substrate, wherein the stiffener ring comprises a reinforcement rib striding across the molding compound.
  • a heat sink is directly bonded to the rear surface of the first semiconductor die, the rear surface of the second semiconductor die, and a top surface of the reinforcement rib through a thermal interface material (TIM) layer.
  • TIM thermal interface material
  • a semiconductor package is defined in claim 15 and includes a package substrate having a top surface and a bottom surface, an interposer mounted on the top surface of the package substrate, a first semiconductor die mounted on the interposer, a stiffener ring secured to the top surface of the package substrate, wherein the stiffener ring encircles the first semiconductor die and a heat sink directly bonded to a rear surface of the first semiconductor die.
  • a stiffener ring is provided that is secured to the top surface of the package substrate together with at least two further features to achieve that the structural rigidity of the electronics package is improved when high thermal stresses occur.
  • these features are that the stiffener ring encircles the first semiconductor die and the second semiconductor die and comprises a reinforcement rib striding across the interposer
  • these features are that a molding compound encapsulating the first semiconductor die and the second semiconductor die is provided and the stiffener ring comprises a reinforcement rib striding across the molding compound
  • these features are that the stiffener ring encircles the first semiconductor die and a heat sink is directly bonded to a rear surface of the first semiconductor die.
  • a stiffener ring secured to the top surface of the package substrate is provided together with two further features that enhance the structural rigidity of the package.
  • a semiconductor package 1a is provided.
  • the semiconductor package 1a may be a 2.5D semiconductor package.
  • the semiconductor package 1a comprises a package substrate 10 having a top surface 10a and a bottom surface 10b.
  • An interposer 20 is mounted on the top surface 10a of the package substrate 10.
  • the interposer 20 may comprise a silicon interposer or an RDL (re-distribution layer) interposer, but is not limited thereto.
  • a plurality of connecting elements 102 may be provided on the bottom surface 10b.
  • the plurality of connecting elements 102 may be sober balls. Through the plurality of connecting elements 102, the semiconductor package 1a may be mounted to a printed circuit board or system board, but is not limited thereto.
  • a first semiconductor die 31 and a second semiconductor die 32 are mounted on a top surface 20a of the interposer 20 in a side-by-side manner.
  • the first semiconductor die 31 and the second semiconductor die 32 may be flip chips with their active surfaces 31a and 32a facing down to the interposer 20.
  • the first semiconductor die 31 and the second semiconductor die 32 may be connected to the interposer 20 through the bumps 310 and bumps 320 on their active surfaces 31a and 32a, respectively.
  • the interposer 20 provides electrical connections between the dies 31, 32 and the package substrate 10, and possibly between the dies 31, 32 themselves.
  • the number of the semiconductor dies in the figures are for illustration purposes only. The number of the semiconductor dies is not limited to two and may exceed two.
  • a plurality of connecting elements 202 are provided on the bottom surface 20b of the interposer 20, a plurality of connecting elements 202 are provided. Through the connecting elements 202, the interposer 20 is electrically connected to the package substrate 10. The first semiconductor die 31 and the second semiconductor die 32 are electrically connected to the package substrate 10 through the interposer 20. In some embodiments, the first semiconductor die 31 and the second semiconductor die 32 may be electrically connected to each other through the interposer 20. According to one embodiment, a stiffener ring 40 is secured to the top surface 10a of the package substrate 10. The stiffener ring 40 may be disposed along the perimeter of the package substrate 10 so as to form a rectangular shape, for example. The stiffener ring 40 encircles the first semiconductor die 31 and the second semiconductor die 32.
  • the stiffener ring 40 may be secured to the top surface 10a of the package substrate 10 by using an adhesive layer, but is not limited thereto.
  • the stiffener ring 40 may be composed of copper, but is not limited thereto.
  • the stiffener ring 40 comprises a reinforcement rib 401 striding across the interposer 20.
  • the reinforcement rib 401 is integrally connected to the stiffener ring 40 through a downset portion 401b.
  • the reinforcement rib 401 extends through a space between the first semiconductor die 31 and the second semiconductor die 32.
  • the reinforcement rib 401 is in direct contact with the top surface 20a of the interposer 20.
  • no molding compound is used to cover the interposer 20, the first semiconductor die 31, and the second semiconductor die 32.
  • the reinforcement rib 401 is interposed between the first semiconductor die 31 and the second semiconductor die 32 from the top view of this embodiment.
  • the reinforcement rib 401 is coplanar with the first semiconductor die 31 and the second semiconductor die 32
  • the semiconductor package 1a may further comprise a heat sink 50.
  • the heat sink 50 may be directly bonded to a rear surface 31b of the first semiconductor die 31, a rear surface 32b of the second semiconductor die 32, and/or a top surface 401a of the reinforcement rib 401 through a thermal interface material (TIM) layer 510.
  • TIM thermal interface material
  • the heat sink 50 is not shown in FIG. 1 .
  • FIG. 4 , FIG. 5, and FIG. 6 illustrate another embodiment of the invention, wherein like numeral numbers designate like regions, layers, or elements.
  • FIG. 4 is a schematic, top view of a semiconductor package according to another embodiment of the invention.
  • FIG. 5 is a schematic, cross-sectional diagram taken alone line I-I' in FIG. 4 .
  • FIG. 6 is a schematic, cross-sectional diagram taken alone line II-II' in FIG. 4 .
  • a semiconductor package 1b is provided.
  • the semiconductor package 1b may be a 2.5D semiconductor package.
  • the semiconductor package 1b comprises a package substrate 10 having a top surface 10a and a bottom surface 10b.
  • An interposer 20 is mounted on the top surface 10a of the package substrate 10.
  • the interposer 20 may comprise a silicon interposer or an RDL interposer.
  • a plurality of connecting elements 102 may be provided on the bottom surface 10b.
  • the plurality of connecting elements 102 may be sober balls.
  • the semiconductor package 1b may be mounted to a printed circuit board or system board.
  • a first semiconductor die 31 and a second semiconductor die 32 are mounted on a top surface 20a of the interposer 20 in a side-by-side manner.
  • the first semiconductor die 31 and the second semiconductor die 32 may be flip chips with their active surfaces 31a and 32a facing down to the interposer 20.
  • the first semiconductor die 31 and the second semiconductor die 32 may be connected to the interposer 20 through the bumps 310 and bumps 320 on their active surfaces 31a and 32a, respectively.
  • the first semiconductor die 31 may comprise an application-specific integrated chip (ASIC) or a microprocessor, but is not limited thereto.
  • the second semiconductor die 32 may comprise a high bandwidth memory (HBM) chip in which a plurality of memory chips having through silicon vias (TSVs) are stacked.
  • the first semiconductor die 31 is disposed in close proximity to the second semiconductor die 32. For example, typically, a gap between first semiconductor die 31 and the second semiconductor die 32 may be smaller than 100 micrometers.
  • a plurality of connecting elements 202 are provided on the bottom surface 20b of the interposer 20, a plurality of connecting elements 202 are provided. Through the connecting elements 202, the interposer 20 is electrically connected to the package substrate 10.
  • the first semiconductor die 31 and the second semiconductor die 32 are electrically connected to the package substrate 10 through the interposer 20.
  • the first semiconductor die 31 and the second semiconductor die 32 may be electrically connected to each other through the interposer 20.
  • a stiffener ring 40 is secured to the top surface 10a of the package substrate 10.
  • the stiffener ring 40 may be disposed along the perimeter of the package substrate 10 so as to form a rectangular shape, for example.
  • the stiffener ring 40 encircles the first semiconductor die 31 and the second semiconductor die 32.
  • the stiffener ring 40 may be secured to the top surface 10a of the package substrate 10 by using an adhesive layer, but is not limited thereto.
  • the stiffener ring 40 may be composed of copper, but is not limited thereto.
  • the stiffener ring 40 comprises two reinforcement ribs 401 striding across the interposer 20.
  • the two reinforcement ribs 401 circumvent the first semiconductor die 31 and the second semiconductor die 32.
  • the reinforcement ribs 401 are integrally connected to the stiffener ring 40 through downset portions 401b.
  • the reinforcement ribs 401 extend along the two opposite side edges of the interposer 20.
  • the reinforcement ribs 401 are in direct contact with the top surface 20a of the interposer 20.
  • no molding compound is used to cover the interposer 20, the first semiconductor die 31, and the second semiconductor die 32.
  • the semiconductor package 1b may further comprise a heat sink 50.
  • the heat sink 50 may be directly bonded to a rear surface 31b of the first semiconductor die 31, a rear surface 32b of the second semiconductor die 32 through a thermal interface material (TIM) layer 510.
  • TIM thermal interface material
  • the heat sink 50 is not shown in FIG. 4 .
  • the heat sink 50 may be also bonded to the reinforcement rib 401 between the first semiconductor die 31 and the second semiconductor die 32, which helps to dissipate heat.
  • the first semiconductor die 31 and/or the second semiconductor die 32 may be in thermal contact with the reinforcement rib 401.
  • the two reinforcement ribs 401 may extend along a direction that is different from the vertical direction as shown in FIG. 4 .
  • the two reinforcement ribs 401 may extend along a horizontal direction along two opposite sides of the each of the first semiconductor die 31 and the second semiconductor die 32.
  • FIG. 7 and FIG. 8 show another embodiment of the invention, wherein like numeral numbers designate like regions, layers, or elements.
  • FIG. 7 is a schematic, top view of a semiconductor package according to another embodiment of the invention.
  • FIG. 8 is a schematic, cross-sectional diagram taken alone line I-I' in FIG. 7 .
  • the semiconductor package 1c may be a 2.5D semiconductor package.
  • the semiconductor package 1c comprises a package substrate 10 having a top surface 10a and a bottom surface 10b.
  • An interposer 20 is mounted on the top surface 10a of the package substrate 10.
  • the interposer 20 may comprise a silicon interposer or an RDL interposer, but is not limited thereto.
  • the stiffener ring 40 comprises three reinforcement ribs 401 striding across the interposer 20.
  • the reinforcement ribs 401 are integrally connected to the stiffener ring 40 through downset portions 401b. Two of the three reinforcement ribs 401 extend along the two opposite side edges of the interposer 20. One of the three reinforcement ribs 401 extends through a space between the first semiconductor die 31 and the second semiconductor die 32. The reinforcement ribs 401 are in direct contact with the top surface 20a of the interposer 20.
  • no molding compound is used to cover the interposer 20, the first semiconductor die 31, and the second semiconductor die 32.
  • the semiconductor package 1c may further comprise a heat sink 50.
  • the heat sink 50 may be directly bonded to a rear surface 31b of the first semiconductor die 31, a rear surface 32b of the second semiconductor die 32 through a thermal interface material (TIM) layer 510.
  • TIM thermal interface material
  • the heat sink 50 is not shown in FIG. 7 .
  • FIG. 9 and FIG. 10 show another embodiment of the invention, wherein like numeral numbers designate like regions, layers, or elements.
  • FIG. 9 is a schematic, top view of a semiconductor package according to another embodiment of the invention.
  • FIG. 10 is a schematic, cross-sectional diagram taken alone line I-I' in FIG. 9 .
  • the stiffener ring 40 comprises multiple reinforcement ribs 401 striding across the interposer 20.
  • the multiple reinforcement ribs 401 may be shaped into frames that encircle the first semiconductor die 31 and the second semiconductor die 32.
  • the reinforcement ribs 401 are integrally connected to the stiffener ring 40 through downset portions 401b.
  • the reinforcement ribs 401 are in direct contact with the top surface 20a of the interposer 20.
  • no molding compound is used to cover the interposer 20, the first semiconductor die 31, and the second semiconductor die 32.
  • the semiconductor package 1d may further comprise a heat sink 50.
  • the heat sink 50 may be directly bonded to a rear surface 31b of the first semiconductor die 31, a rear surface 32b of the second semiconductor die 32 through a thermal interface material (TIM) layer 510.
  • TIM thermal interface material
  • the heat sink 50 is not shown in FIG. 9 .
  • FIG. 11, FIG. 12 , and FIG. 13 show another embodiment of the invention, wherein like numeral numbers designate like regions, layers, or elements.
  • FIG. 11 is a schematic, top view of a semiconductor package according to another embodiment of the invention.
  • FIG. 12 is a schematic, cross-sectional diagram taken alone line I-I' in FIG. 11 .
  • FIG. 13 is a schematic, cross-sectional diagram taken alone line II-II' in FIG. 11 .
  • the semiconductor package If may be a 2.5D semiconductor package.
  • the semiconductor package If comprises a package substrate 10 having a top surface 10a and a bottom surface 10b.
  • An interposer 20 is mounted on the top surface 10a of the package substrate 10.
  • the interposer 20 may comprise a silicon interposer or an RDL interposer, but is not limited thereto.
  • a plurality of connecting elements 102 may be provided on the bottom surface 10b.
  • the plurality of connecting elements 102 may be sober balls.
  • the semiconductor package If may be mounted to a printed circuit board or system board, but is not limited thereto.
  • a first semiconductor die 31 and a second semiconductor die 32 are mounted on a top surface 20a of the interposer 20 in a side-by-side manner.
  • the first semiconductor die 31 and the second semiconductor die 32 may be flip chips with their active surfaces 31a and 32a facing down to the interposer 20.
  • the first semiconductor die 31 and the second semiconductor die 32 may be connected to the interposer 20 through the bumps 310 and bumps 320 on their active surfaces 31a and 32a, respectively.
  • the first semiconductor die 31 may comprise an application-specific integrated chip (ASIC) or a microprocessor, but is not limited thereto.
  • the second semiconductor die 32 may comprise a high bandwidth memory (HBM) chip in which a plurality of memory chips having through silicon vias (TSVs) are stacked. It is understood that the first semiconductor die 31 and the second semiconductor die 32 may be both ASIC or both System-on-Chip (SoC) chip.
  • the first semiconductor die 31 and the second semiconductor die 32 may comprise a SoC and a DRAM die.
  • the first semiconductor die 31 and the second semiconductor die 32 may comprise an ASIC and an HBM chip.Although only two semiconductor dies are illustrated in the figures, it is understood that the semiconductor package may comprise more than two semiconductor dies in other embodiments.
  • a plurality of connecting elements 202 are provided on the bottom surface 20b of the interposer 20, a plurality of connecting elements 202 are provided. Through the connecting elements 202, the interposer 20 is electrically connected to the package substrate 10. The first semiconductor die 31 and the second semiconductor die 32 are electrically connected to the package substrate 10 through the interposer 20. In some embodiments, the first semiconductor die 31 and the second semiconductor die 32 may be electrically connected to each other through the interposer 20. According to one embodiment, a molding compound 60 is provided to encapsulate the first semiconductor die 31 and the second semiconductor die 32. The rear surface 31b of the first semiconductor die 31 and the rear surface 32b of the second semiconductor die 32 are not covered by the molding compound 60.
  • a stiffener ring 40 is secured to the top surface 10a of the package substrate 10.
  • the stiffener ring 40 may be disposed along the perimeter of the package substrate 10 so as to form a rectangular shape, for example.
  • the stiffener ring 40 encircles the first semiconductor die 31 and the second semiconductor die 32.
  • the stiffener ring 40 may be secured to the top surface 10a of the package substrate 10 by using an adhesive layer, but is not limited thereto.
  • the stiffener ring 40 may be composed of copper, but is not limited thereto.
  • the stiffener ring 40 comprises two reinforcement ribs 401 striding across the molding compound 60.
  • the reinforcement ribs 401 are integrally connected to the stiffener ring 40 through downset portions 401b.
  • the reinforcement ribs 401 extend along the two opposite side edges of the interposer 20.
  • the reinforcement ribs 401 are in direct contact with the top surface 20a of the molding compound 60.
  • the semiconductor package If may further comprise a heat sink 50.
  • the heat sink 50 may be directly bonded to a rear surface 31b of the first semiconductor die 31, a rear surface 32b of the second semiconductor die 32, and a top surface 401a of the reinforcement rib 401 through a thermal interface material (TIM) layer 510.
  • TIM thermal interface material
  • the reinforcement ribs 401 may partially overlap with the rear surface of the first semiconductor die 31 or the second semiconductor die 32.
  • the heat sink 50 is not shown in FIG. 11 .
  • the reinforcement ribs 401 may be in direct contact with the rear surface of the first semiconductor die 31 or the second semiconductor die 32.
  • the reinforcement ribs 401 may be a straight-line shaped rib across the molding compound 60 when viewed from the above. However, it is understood that the reinforcement ribs 401 may have other shapes. For example, in FIG. 19 , the reinforcement ribs 401 are bent so as to form an octagonal structure with the surrounding stiffener ring 40. Such octagonal structure may provide better structural rigidity for the semiconductor package.
  • FIG. 14 and FIG. 15 show another embodiment of the invention, wherein like numeral numbers designate like regions, layers, or elements.
  • FIG. 14 is a schematic, top view of a semiconductor package according to another embodiment of the invention.
  • FIG. 15 is a schematic, cross-sectional diagram taken alone line I-I' in FIG. 14 .
  • a semiconductor package 1g is provided.
  • the semiconductor package 1g may be a 2.5D semiconductor package.
  • the semiconductor package 1g comprises a package substrate 10 having a top surface 10a and a bottom surface 10b.
  • An interposer 20 is mounted on the top surface 10a of the package substrate 10.
  • the interposer 20 may comprise a silicon interposer or an RDL interposer, but is not limited thereto.
  • the molding compound 60 is provided to encapsulate the first semiconductor die 31 and the second semiconductor die 32.
  • the rear surface 31b of the first semiconductor die 31 and the rear surface 32b of the second semiconductor die 32 are not covered by the molding compound 60.
  • the stiffener ring 40 comprises two reinforcement ribs 401' and 401" striding across the molding compound 60.
  • the reinforcement ribs 401' and 401" are integrally connected to the stiffener ring 40 through downset portions 401b.
  • An asymmetric reinforcement rib configuration may be employed.
  • the three reinforcement rib 401' has a greater width (or surface area) than that of the reinforcement rib 401".
  • the reinforcement rib 401' may completely overlap with the rear surface 31b of the first semiconductor die 31.
  • the reinforcement rib 401" may extend along a side edge of the interposer 20 and may not overlap with the second semiconductor die 32 when viewed from the above.
  • FIG. 16 and FIG. 17 show another embodiment of the invention, wherein like numeral numbers designate like regions, layers, or elements.
  • FIG. 16 is a schematic, top view of a semiconductor package according to another embodiment of the invention.
  • FIG. 17 is a schematic, cross-sectional diagram taken alone line I-I' in FIG. 16 .
  • a semiconductor package 1h is provided.
  • the semiconductor package 1h may be a 2.5D semiconductor package.
  • the semiconductor package 1h comprises a package substrate 10 having a top surface 10a and a bottom surface 10b.
  • An interposer 20 is mounted on the top surface 10a of the package substrate 10.
  • the interposer 20 may comprise a silicon interposer or an RDL interposer, but is not limited thereto.
  • the molding compound 60 is provided to encapsulate the first semiconductor die 31 and the second semiconductor die 32.
  • the rear surface 31b of the first semiconductor die 31 and the rear surface 32b of the second semiconductor die 32 are not covered by the molding compound 60.
  • the stiffener ring 40 comprises two reinforcement ribs 401 striding across the interposer 20.
  • the reinforcement ribs 401 are integrally connected to the stiffener ring 40 through downset portions 401b.
  • the reinforcement ribs 401 are in direct contact with the top surface 20a of the interposer 20 and the peripheral sidewalls of the molding compound 60.
  • the reinforcement rib 401, the first semiconductor die 31 and the second semiconductor die 32 may be in thermal contact with the heat sink 50 through the thermal interface material (TIM) layer 510.
  • TIM thermal interface material
  • FIG. 21 and FIG. 22 show another embodiment of the invention, wherein like numeral numbers designate like regions, layers, or elements.
  • FIG. 21 is a schematic, top view of a semiconductor package according to yet another embodiment of the invention.
  • FIG. 22 is a schematic, cross-sectional diagram taken alone line I-I' in FIG. 21 .
  • a semiconductor package 1i is provided.
  • the semiconductor package 1i may comprise a 2. 5D fan-out semiconductor package 3.
  • the semiconductor package 1i comprises a package substrate 10 having a top surface 10a and a bottom surface 10b.
  • the 2.5D fan-out semiconductor package 3 is mounted on the top surface 10a.
  • the first semiconductor die 31 and the second semiconductor die 32 are interconnected through a re-distribution layer (RDL) structure 21.
  • the RDL structure 21 is formed on the molding compound 60 and the active surfaces 31a and 32a of the first semiconductor die 31 and the second semiconductor die 32 to directly connect to the bond pads of the first semiconductor die 31 and the second semiconductor die 32.
  • the first semiconductor die 31 may comprise an application-specific integrated chip (ASIC) or a microprocessor, but is not limited thereto.
  • the second semiconductor die 32 may comprise a high bandwidth memory (HBM) chip in which a plurality of memory chips having through silicon vias (TSVs) are stacked.
  • HBM high bandwidth memory
  • TSVs through silicon vias
  • a plurality of connecting elements 202 are provided on the bottom surface 20b of the RDL structure 21, a plurality of connecting elements 202 are provided. Through the connecting elements 202, the RDL structure 21 is electrically connected to the package substrate 10.
  • the molding compound 60 is provided to encapsulate the first semiconductor die 31 and the second semiconductor die 32.
  • the rear surface 31b of the first semiconductor die 31 and the rear surface 32b of the second semiconductor die 32 are not covered by the molding compound 60.
  • a stiffener ring 40 is secured to the top surface 10a of the package substrate 10.
  • the stiffener ring 40 may be disposed along the perimeter of the package substrate 10 so as to form a rectangular shape, for example.
  • the stiffener ring 40 encircles the first semiconductor die 31 and the second semiconductor die 32.
  • the stiffener ring 40 may be secured to the top surface 10a of the package substrate 10 by using an adhesive layer, but is not limited thereto.
  • the stiffener ring 40 may be composed of copper, but is not limited thereto.
  • the stiffener ring 40 may comprise two reinforcement ribs 401 striding across the molding compound 60. As can be seen in FIG. 21 , the reinforcement ribs 401 are integrally connected to the stiffener ring 40 through downset portions 401b. The reinforcement ribs 401 extend along the two opposite side edges of the 2.5D fan-out semiconductor package 3. The reinforcement ribs 401 are in direct contact with the top surface 20a of the molding compound 60.
  • the heat sink 50 may be directly bonded to a rear surface 31b of the first semiconductor die 31, a rear surface 32b of the second semiconductor die 32, and a top surface 401a of the reinforcement rib 401 through the thermal interface material layer 510.
  • the reinforcement ribs 401 may partially overlap with the rear surface of the first semiconductor die 31 or the second semiconductor die 32.
  • the heat sink 50 is not shown in FIG. 21 .
  • the reinforcement ribs 401 may be in direct contact with the rear surface of the first semiconductor die 31 or the second semiconductor die 32.
  • the reinforcement ribs 401 may be a straight-line shaped rib across the molding compound 60 when viewed from the above. However, it is understood that the reinforcement ribs 401 may have other shapes.

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US15/863,984 US10573579B2 (en) 2017-03-08 2018-01-08 Semiconductor package with improved heat dissipation

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US20180261528A1 (en) 2018-09-13
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EP3373331B1 (de) 2020-11-04
US10573579B2 (en) 2020-02-25
TW201843806A (zh) 2018-12-16

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