EP2831918A4 - Verfahren zur ono-integration in eine logische cmos-strömung - Google Patents

Verfahren zur ono-integration in eine logische cmos-strömung

Info

Publication number
EP2831918A4
EP2831918A4 EP13767491.7A EP13767491A EP2831918A4 EP 2831918 A4 EP2831918 A4 EP 2831918A4 EP 13767491 A EP13767491 A EP 13767491A EP 2831918 A4 EP2831918 A4 EP 2831918A4
Authority
EP
European Patent Office
Prior art keywords
ono
integration
logic cmos
cmos flow
logic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP13767491.7A
Other languages
English (en)
French (fr)
Other versions
EP2831918A1 (de
Inventor
Krishnaswamy Ramkumar
Bo Jin
Fredrick Jenne
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Cypress Semiconductor Corp
Original Assignee
Cypress Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US13/434,347 external-priority patent/US9102522B2/en
Application filed by Cypress Semiconductor Corp filed Critical Cypress Semiconductor Corp
Priority to EP16167775.2A priority Critical patent/EP3166147A3/de
Priority to EP21160971.4A priority patent/EP3866199A1/de
Publication of EP2831918A1 publication Critical patent/EP2831918A1/de
Publication of EP2831918A4 publication Critical patent/EP2831918A4/de
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324—Gate electrodes for transistors with a floating gate
    • H01L29/42328—Gate electrodes for transistors with a floating gate with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H01L29/7926—Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
EP13767491.7A 2012-03-29 2013-03-13 Verfahren zur ono-integration in eine logische cmos-strömung Withdrawn EP2831918A4 (de)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP16167775.2A EP3166147A3 (de) 2012-03-29 2013-03-13 Verfahren zur ono-integration in einen cmos logik-prozess
EP21160971.4A EP3866199A1 (de) 2012-03-29 2013-03-13 Verfahren zur ono-integration in einen cmos logik prozess

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/434,347 US9102522B2 (en) 2009-04-24 2012-03-29 Method of ONO integration into logic CMOS flow
PCT/US2013/030874 WO2013148196A1 (en) 2012-03-29 2013-03-13 Method of ono integration into logic cmos flow

Related Child Applications (2)

Application Number Title Priority Date Filing Date
EP21160971.4A Division EP3866199A1 (de) 2012-03-29 2013-03-13 Verfahren zur ono-integration in einen cmos logik prozess
EP16167775.2A Division EP3166147A3 (de) 2012-03-29 2013-03-13 Verfahren zur ono-integration in einen cmos logik-prozess

Publications (2)

Publication Number Publication Date
EP2831918A1 EP2831918A1 (de) 2015-02-04
EP2831918A4 true EP2831918A4 (de) 2015-11-18

Family

ID=49261024

Family Applications (3)

Application Number Title Priority Date Filing Date
EP16167775.2A Withdrawn EP3166147A3 (de) 2012-03-29 2013-03-13 Verfahren zur ono-integration in einen cmos logik-prozess
EP21160971.4A Pending EP3866199A1 (de) 2012-03-29 2013-03-13 Verfahren zur ono-integration in einen cmos logik prozess
EP13767491.7A Withdrawn EP2831918A4 (de) 2012-03-29 2013-03-13 Verfahren zur ono-integration in eine logische cmos-strömung

Family Applications Before (2)

Application Number Title Priority Date Filing Date
EP16167775.2A Withdrawn EP3166147A3 (de) 2012-03-29 2013-03-13 Verfahren zur ono-integration in einen cmos logik-prozess
EP21160971.4A Pending EP3866199A1 (de) 2012-03-29 2013-03-13 Verfahren zur ono-integration in einen cmos logik prozess

Country Status (6)

Country Link
EP (3) EP3166147A3 (de)
JP (1) JP6328607B2 (de)
KR (2) KR20190082327A (de)
CN (2) CN108899273B (de)
TW (2) TWI599020B (de)
WO (1) WO2013148196A1 (de)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9102522B2 (en) 2009-04-24 2015-08-11 Cypress Semiconductor Corporation Method of ONO integration into logic CMOS flow
US8071453B1 (en) 2009-04-24 2011-12-06 Cypress Semiconductor Corporation Method of ONO integration into MOS flow
US8883624B1 (en) 2013-09-27 2014-11-11 Cypress Semiconductor Corporation Integration of a memory transistor into high-K, metal gate CMOS process flow
CN104617100A (zh) * 2015-01-30 2015-05-13 武汉新芯集成电路制造有限公司 Sonos存储器结构及其制作方法
US9218978B1 (en) * 2015-03-09 2015-12-22 Cypress Semiconductor Corporation Method of ONO stack formation
US10020317B2 (en) * 2015-08-31 2018-07-10 Cypress Semiconductor Corporation Memory device with multi-layer channel and charge trapping layer
US10242996B2 (en) * 2017-07-19 2019-03-26 Cypress Semiconductor Corporation Method of forming high-voltage transistor with thin gate poly
CN110416221B (zh) * 2019-07-31 2022-02-22 上海华力微电子有限公司 半导体器件的形成方法
US11488977B2 (en) 2020-04-14 2022-11-01 Yangtze Memory Technologies Co., Ltd. Three-dimensional memory devices and methods for forming the same
TWI773086B (zh) * 2020-11-17 2022-08-01 大陸商長江存儲科技有限責任公司 用於形成立體（３ｄ）記憶體元件的方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050173766A1 (en) * 2004-01-05 2005-08-11 Samsung Electronics Co., Ltd. Semiconductor memory and manufacturing method thereof
US20060115978A1 (en) * 2004-11-30 2006-06-01 Michael Specht Charge-trapping memory cell and method for production
US8063434B1 (en) * 2007-05-25 2011-11-22 Cypress Semiconductor Corporation Memory transistor with multiple charge storing layers and a high work function gate electrode
US8071453B1 (en) * 2009-04-24 2011-12-06 Cypress Semiconductor Corporation Method of ONO integration into MOS flow

Family Cites Families (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3651689B2 (ja) * 1993-05-28 2005-05-25 株式会社東芝 Ｎａｎｄ型不揮発性半導体記憶装置及びその製造方法
US6093606A (en) * 1998-03-05 2000-07-25 Taiwan Semiconductor Manufacturing Company Method of manufacture of vertical stacked gate flash memory device
JP3955409B2 (ja) * 1999-03-17 2007-08-08 株式会社ルネサステクノロジ 半導体記憶装置
JP3459240B2 (ja) * 2001-06-22 2003-10-20 富士雄 舛岡 半導体記憶装置
JP2004095918A (ja) * 2002-08-30 2004-03-25 Fasl Japan Ltd 半導体記憶装置及び半導体装置の製造方法
JP4489359B2 (ja) * 2003-01-31 2010-06-23 株式会社ルネサステクノロジ 不揮発性半導体記憶装置
DE10345237B4 (de) * 2003-09-29 2005-11-10 Infineon Technologies Ag Verfahren zur Herstellung von Charge-Trapping-Speicherbauelementen
US6946349B1 (en) * 2004-08-09 2005-09-20 Chartered Semiconductor Manufacturing Ltd. Method for integrating a SONOS gate oxide transistor into a logic/analog integrated circuit having several gate oxide thicknesses
KR100583969B1 (ko) * 2004-08-13 2006-05-26 삼성전자주식회사 부분 소노스 게이트 구조를 갖는 비휘발성 메모리소자의제조방법
US7393733B2 (en) * 2004-12-01 2008-07-01 Amberwave Systems Corporation Methods of forming hybrid fin field-effect transistor structures
US7439594B2 (en) * 2006-03-16 2008-10-21 Micron Technology, Inc. Stacked non-volatile memory with silicon carbide-based amorphous silicon thin film transistors
US8816422B2 (en) * 2006-09-15 2014-08-26 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-trapping layer flash memory cell
US8772858B2 (en) * 2006-10-11 2014-07-08 Macronix International Co., Ltd. Vertical channel memory and manufacturing method thereof and operating method using the same
JP4772656B2 (ja) * 2006-12-21 2011-09-14 株式会社東芝 不揮発性半導体メモリ
JPWO2008117798A1 (ja) * 2007-03-26 2010-07-15 東京エレクトロン株式会社 窒化珪素膜の形成方法、不揮発性半導体メモリ装置の製造方法、不揮発性半導体メモリ装置およびプラズマ処理装置
US7670963B2 (en) * 2007-05-25 2010-03-02 Cypress Semiconductor Corportion Single-wafer process for fabricating a nonvolatile charge trap memory device
US8614124B2 (en) * 2007-05-25 2013-12-24 Cypress Semiconductor Corporation SONOS ONO stack scaling
US8643124B2 (en) * 2007-05-25 2014-02-04 Cypress Semiconductor Corporation Oxide-nitride-oxide stack having multiple oxynitride layers
KR100880228B1 (ko) * 2007-10-17 2009-01-28 주식회사 동부하이텍 Ｓｏｎｏｓ 반도체 소자의 제조방법
KR101226685B1 (ko) * 2007-11-08 2013-01-25 삼성전자주식회사 수직형 반도체 소자 및 그 제조 방법.
US20090152621A1 (en) * 2007-12-12 2009-06-18 Igor Polishchuk Nonvolatile charge trap memory device having a high dielectric constant blocking region
JP2011124240A (ja) * 2008-03-31 2011-06-23 Tokyo Electron Ltd Ｍｏｓ型半導体メモリ装置、その製造方法およびコンピュータ読み取り可能な記憶媒体
JP5288877B2 (ja) * 2008-05-09 2013-09-11 株式会社東芝 不揮発性半導体記憶装置
JP5356005B2 (ja) * 2008-12-10 2013-12-04 株式会社東芝 不揮発性半導体記憶装置及びその製造方法
KR101573697B1 (ko) * 2009-02-11 2015-12-02 삼성전자주식회사 수직 폴딩 구조의 비휘발성 메모리 소자 및 그 제조 방법
JP5531259B2 (ja) * 2009-03-19 2014-06-25 株式会社東芝 半導体装置及びその製造方法
KR101548674B1 (ko) * 2009-08-26 2015-09-01 삼성전자주식회사 3차원 반도체 메모리 장치 및 그 제조 방법
JP5534748B2 (ja) * 2009-08-25 2014-07-02 株式会社東芝 不揮発性半導体記憶装置及びその製造方法
JP5121869B2 (ja) * 2010-03-23 2013-01-16 株式会社東芝 不揮発性半導体記憶装置の製造方法
US9536970B2 (en) * 2010-03-26 2017-01-03 Samsung Electronics Co., Ltd. Three-dimensional semiconductor memory devices and methods of fabricating the same
KR101756227B1 (ko) * 2010-08-13 2017-07-10 삼성전자 주식회사 수직 채널 패턴을 포함하는 반도체 소자
KR20120029291A (ko) * 2010-09-16 2012-03-26 삼성전자주식회사 반도체 소자 및 그 제조 방법

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050173766A1 (en) * 2004-01-05 2005-08-11 Samsung Electronics Co., Ltd. Semiconductor memory and manufacturing method thereof
US20060115978A1 (en) * 2004-11-30 2006-06-01 Michael Specht Charge-trapping memory cell and method for production
US8063434B1 (en) * 2007-05-25 2011-11-22 Cypress Semiconductor Corporation Memory transistor with multiple charge storing layers and a high work function gate electrode
US8071453B1 (en) * 2009-04-24 2011-12-06 Cypress Semiconductor Corporation Method of ONO integration into MOS flow

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
JOO HYUNG YOU ET AL: "Effect of the trap density and distribution of the silicon nitride layer on the retention characteristics of charge trap flash memory devices", SIMULATION OF SEMICONDUCTOR PROCESSES AND DEVICES (SISPAD), 2011 INTERNATIONAL CONFERENCE ON, IEEE, 8 September 2011 (2011-09-08), pages 199 - 202, XP031972658, ISBN: 978-1-61284-419-0, DOI: 10.1109/SISPAD.2011.6035085 *
PEIQI XUAN ET AL: "FinFET SONOS Flash Memory for Embedded Applications", INTERNATIONAL ELECTRON DEVICES MEETING 2003. IEDM. TECHNICAL DIGEST. WASHINGTON, DC, DEC 8 - 10, 2003; [INTERNATIONAL ELECTRON DEVICES MEETING], NEW YORK, NY : IEEE, US, 8 December 2003 (2003-12-08), pages 609 - 612, XP010684085, ISBN: 978-0-7803-7872-8 *
See also references of WO2013148196A1 *

Also Published As

Publication number Publication date
CN104321877B (zh) 2018-09-14
TWI648843B (zh) 2019-01-21
EP3166147A3 (de) 2017-08-16
JP6328607B2 (ja) 2018-05-23
EP2831918A1 (de) 2015-02-04
KR20190082327A (ko) 2019-07-09
TW201743437A (zh) 2017-12-16
CN108899273B (zh) 2024-02-09
WO2013148196A1 (en) 2013-10-03
KR102079835B1 (ko) 2020-02-20
JP2015512567A (ja) 2015-04-27
CN108899273A (zh) 2018-11-27
CN104321877A (zh) 2015-01-28
TW201347150A (zh) 2013-11-16
EP3166147A2 (de) 2017-05-10
EP3866199A1 (de) 2021-08-18
TWI599020B (zh) 2017-09-11
KR20150105186A (ko) 2015-09-16

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