EP2815430A1 - Ensemble à semi-conducteurs d'un capteur de courant disposé dans un semi-conducteur de puissance - Google Patents

Ensemble à semi-conducteurs d'un capteur de courant disposé dans un semi-conducteur de puissance

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Publication number
EP2815430A1
EP2815430A1 EP13702607.6A EP13702607A EP2815430A1 EP 2815430 A1 EP2815430 A1 EP 2815430A1 EP 13702607 A EP13702607 A EP 13702607A EP 2815430 A1 EP2815430 A1 EP 2815430A1
Authority
EP
European Patent Office
Prior art keywords
region
transistor cells
semiconductor device
sensor
cells
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP13702607.6A
Other languages
German (de)
English (en)
Other versions
EP2815430B1 (fr
EP2815430B8 (fr
Inventor
Thomas Jacke
Timm Hoehr
Christian Pluntke
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Robert Bosch GmbH
Infineon Technologies AG
Original Assignee
Robert Bosch GmbH
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Filing date
Publication date
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Publication of EP2815430A1 publication Critical patent/EP2815430A1/fr
Publication of EP2815430B1 publication Critical patent/EP2815430B1/fr
Application granted granted Critical
Publication of EP2815430B8 publication Critical patent/EP2815430B8/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H01L27/0211—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique adapted for requirements of temperature
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01H—MEASUREMENT OF MECHANICAL VIBRATIONS OR ULTRASONIC, SONIC OR INFRASONIC WAVES
    • G01H5/00—Measuring propagation velocity of ultrasonic, sonic or infrasonic waves, e.g. of pressure waves
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N29/00—Investigating or analysing materials by the use of ultrasonic, sonic or infrasonic waves; Visualisation of the interior of objects by transmitting ultrasonic or sonic waves through the object
    • G01N29/04—Analysing solids
    • G01N29/07—Analysing solids by measuring propagation velocity or propagation time of acoustic waves
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N29/00—Investigating or analysing materials by the use of ultrasonic, sonic or infrasonic waves; Visualisation of the interior of objects by transmitting ultrasonic or sonic waves through the object
    • G01N29/44—Processing the detected response signal, e.g. electronic circuits specially adapted therefor
    • G01N29/4463—Signal correction, e.g. distance amplitude correction [DAC], distance gain size [DGS], noise filtering
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N29/00—Investigating or analysing materials by the use of ultrasonic, sonic or infrasonic waves; Visualisation of the interior of objects by transmitting ultrasonic or sonic waves through the object
    • G01N29/44—Processing the detected response signal, e.g. electronic circuits specially adapted therefor
    • G01N29/46—Processing the detected response signal, e.g. electronic circuits specially adapted therefor by spectral analysis, e.g. Fourier analysis or wavelet analysis
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S15/00—Systems using the reflection or reradiation of acoustic waves, e.g. sonar systems
    • G01S15/02—Systems using the reflection or reradiation of acoustic waves, e.g. sonar systems using reflection of acoustic waves
    • G01S15/06—Systems determining the position data of a target
    • G01S15/08—Systems for measuring distance only
    • G01S15/10—Systems for measuring distance only using transmission of interrupted, pulse-modulated waves
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
    • G01S7/52—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S15/00
    • G01S7/523—Details of pulse systems
    • G01S7/526—Receivers
    • G01S7/53—Means for transforming coordinates or for evaluating data, e.g. using computers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET

Definitions

  • the invention relates to a semiconductor device for a current sensor in a semiconductor device for a current sensor in a power semiconductor
  • IGBT Insulated Gate Bipolar Transistor
  • Power semiconductors are usually made as a vertical structure and have a plurality of transistor cells.
  • gate and emitter structures are formed on the front side of a semiconductor substrate, which are connected via at least one p-n junction with the collector layer formed on the back as full-area metallization.
  • this cell structure repeats over a large area of the substrate so that high currents can be switched. It should be noted, however, that short circuit or overload conditions are avoided. So it is known from the general state of the art, at the output terminal a shunt
  • the sensor port is within the emitter region and is completely or partially filled with emitter cells.
  • the embedding of the sensor cells in the main emitter is very narrow and it can be expected that the behavior of the sensor cells differs only slightly from that of the main emitter cells. But through that
  • Size ratio of emitter terminal and sensor terminal is a fixed ratio of sensor current to main current.
  • the case of only partial filling offers the advantage of making this ratio more free, but the narrow embedding is lost and there are cell-free areas in which a charge carrier plasma also builds up in the conducting state.
  • the charge carriers flowing out through the emitter in the case of a shutdown do not overload the individual transistor cells.
  • the charge carrier species flowing out through the emitter is given through holes.
  • the risk of overloading and the triggering of a latch-up exists especially for the cells located at the edges of the sense area and the main emitter area, since a charge carrier plasma also forms in the cell-free areas without emitter contacts.
  • This intermediate region (cell-free region) containing no cells exists on the one hand with incomplete filling of the sensor attachment, but it also results from the necessity of having the two
  • a circuit arrangement for a power semiconductor which comprises on a substrate a multiple arrangement of transistor cells with insulated gate electrode whose emitter terminals are connected in a first region via a first conductive layer with at least one output terminal and their emitter terminals in one second region are connected via a second conductive layer with at least one sensor terminal.
  • the sensor terminal is arranged outside a first cell area boundary, which encloses the transistor cells of the first area and the transistor cells of the second area.
  • a trench structure belonging to the first cell area boundary is formed, to which a doped one connected to the first conductive layer is connected in the direction of an outer edge of the substrate Layer connects and further continues between the transistor cells of the first region and the transistor cells of the second region.
  • the emitter consisting of the IGBT cells is divided into two cell groups.
  • main cells are formed which are connected to the emitter output by means of the first conductive layer.
  • This cell group occupies most of the substrate area of the circuit.
  • the smaller part connected to the second conductive layer is provided as sensor cells, and serves as a current sensor, so that a voltage signal can be generated via an external resistor, which can be further processed for the detection of short-circuit and overcurrents.
  • the doped region connected to the first conductive layer serves to derive the holes draining during the turn-off process, so that they do not stress the adjacent main cells, which could lead to an increased risk of latching events and thus to the destruction of the chip.
  • connection of the sensor outside the active cell area is placed behind the cell area boundary.
  • the holes originating from this connection region are removed via the doped region connected to the conductive layer of the main emitter.
  • size and shape of the sensor area can be designed independently of the size and shape of the sensor connection.
  • the transistor cells of the second region are arranged in the form of an arbitrary polygon, preferably in the form of a semicircle, or a polygon approaching a semicircle, or a rectangle or a square.
  • the transistor cells of the first region enclose the transistor cells of the second region at least partially, preferably on three sides. According to a further embodiment of the invention, the transistor cells of the first region completely surround the transistor cells of the second region.
  • the transistor cells of the second region are arranged spatially separated from the transistor cells of the first region.
  • the current sensor cells are not tightly embedded in the main cells, but surrounded by their own cell area boundary far away from them. This corresponds to a separated smaller IGBT semiconductor whose plasma interacts little or not at all with the main IGBT in the switched-on state or during the switching processes, depending on the distance. Nevertheless, both parts are still to be considered as an IGBT chip because they are surrounded towards the edge of the chip by a common edge termination structure.
  • the sensor connection is arranged as a metallization over an insulating layer whose layer thickness is greater than that of a gate dielectric.
  • the sensor port can be placed anywhere above a thick oxide.
  • the transistor cells of the second area are surrounded by a second cell area boundary.
  • This embodiment is used in particular when the sensor cells are arranged far away from the main cells.
  • the sensor terminal and the transistor cells of the second area are arranged outside the cell area boundary.
  • the second conductive layer may have a notch in the area of the cell area boundary, in which the first conductive layer is connected to the doped layer. This leads to a further improvement of the dissipation of the effluent during shutdown holes.
  • Fig. 1 transistor cells in a cross-sectional view
  • FIG. 2a shows a semiconductor device according to the invention in a plan view according to a first embodiment of the invention
  • FIG. 2b shows a semiconductor device according to the invention in a further plan view according to the first embodiment of the invention.
  • FIG. 3 is a further schematic representation of the embodiment of FIG. 2a;
  • FIG. 4 shows a semiconductor device according to the invention in a plan view according to a further embodiment of the invention
  • FIG. 5 shows a semiconductor device according to the invention in a plan view according to a further embodiment of the invention.
  • FIG. 6 shows a semiconductor device according to the invention in a plan view according to a further embodiment of the invention.
  • Fig. 7 shows a semiconductor device according to the invention in a plan view according to another embodiment of the invention.
  • Fig. 8 shows a semiconductor device according to the invention in a plan view according to another embodiment of the invention.
  • identical or equivalent elements are provided with identical reference numerals.
  • FIG. 1 shows a section of a circuit arrangement 1 which comprises a base cell for a plurality of insulated gate transistor cells 2
  • a substrate 4 which is doped, for example, with p +, on a rear side comprises a collector terminal 5, which is usually applied as a metal layer.
  • a collector terminal 5 Over the collector terminal 5 and the substrate 4, an in this example n-doped buffer layer 6 is applied to the one n-doped epitaxial layer 7 follows.
  • p-doped wells 8 are arranged for example by ion implantation, in each of which two n-doped islands 9 are arranged, which are partially covered by an emitter terminal 10 together with the p-doped well 8.
  • the gate electrode 3 is of an insulating layer formed of silicon oxide
  • Surrounded 1 which may be arranged outside the transistor cell 2.
  • an n + pnp + structure is obtained for an n-channel IGBT.
  • IGBT types for example a p-channel IGBT or an IGBT with a vertical structure.
  • circuit arrangement 1 according to a first embodiment of the invention will be described.
  • the circuit arrangement 1 is shown in a plan view, i. shown on the top with the emitter terminals 10.
  • the circuit arrangement 1 comprises a plurality of
  • Transistor cells 2 which are arranged in a first region 12 and in a second region 13.
  • the arrangement shown in Fig. 2a is to be understood only as an example.
  • the transistor cells 2 cover the first region 12 and the second region, respectively
  • the transistor cells 2 of the first region 12 are connected in parallel and are used for the power semiconductor.
  • Transistor cells 2 of the second region 13 are also connected in parallel and are used for a current sensor, as explained in more detail below. tert.
  • the transistor cells 2 of the first region 12 may be called main cells and those of the second region 13 may be referred to as sensor cells.
  • the transistor cells 2 of the first region 12 and the transistor cells 2 of the second region 13 are surrounded by a first cell area boundary, wherein
  • the Cell area boundary is provided with the reference numeral 14.
  • the first cell area boundary 14 is formed in the form of a trench in the substrate. However, it is also possible to use a double trench structure, which is formed from two trenches running side by side in the substrate.
  • the area outside the first cell area boundary 14 is provided with a doped layer 15, which in the embodiment shown is a p-doped layer.
  • the doped layer 15 is shown in FIG. 2a as a hatched area.
  • the contacting of the transistor cells 2 of the first region 12 and of the transistor cells 2 of the second region 13 will be explained in more detail below.
  • the contacting takes place via metallization layers, which connect the emitter terminals 10 according to FIG.
  • the transistor cells 2 of the first region 12 and the transistor cells 2 of the second region 13 as well as the p-doped layer 15 are not shown for better representability.
  • the emitter terminals of the transistor cells 2 of the first region 12 are connected via a first conductive layer 16.
  • the first conductive layer 16 can serve as output of the power transistor via suitable output terminals, in which the outputs of the transistor cells 2 of the first area 12 are provided.
  • the emitter terminals 10 of the transistor cells 2 of the second area 13 are connected via a second conductive layer 17 to at least one sensor terminal.
  • the sensor port can be connected to an external resistor via a bond wire, as explained below.
  • the second conductive layer 17 also functions as a sensor terminal.
  • the sensor connection is indicated schematically in FIG. 1 by reference numeral 18. In this way, an electrical connection is established between the emitter terminals of the transistor cells 2 of the second area 13 and the sensor terminal 18. As can be seen from FIG. 2b, there is a gap between the first conductive layer 16 and the second conductive layer 17, so that the emitter terminals of these regions are not connected to one another.
  • the p-doped layer 15 which is arranged on an outer edge of the first edge structure 14, is located below the sensor connection 18. This area is connected to the first conductive layer 16 via the contacts 19. As a result, the p-doped layer 15 may allow the holes drained during the turn-off process to be dissipated so that they do not stress the adjacent cells of the transistor cells 2 of the first region 12.
  • Fig. 3 the circuit arrangement 1 according to FIG. 1, Fig. 2a and 2b is summarized again schematically.
  • the transistor cells 2 of the first region 12 form the main cell IGBT 21.
  • the transistor cells 2 of the second region 13 form the sensor cell IGBT 22.
  • the respective collector terminals of the two IGBTs can be connected to a terminal 26 which is the
  • the emitter terminal 10 of the main cell IGBT 21 is connected to the output terminal 25.
  • the emitter terminal 10 of the sensor cell IGBT 22 is connected via the sensor terminal 18 to a component, which may be, for example, an external ohmic resistor 23, wherein a short-circuit or an overload condition can be detected at the output terminal 25 via the signal 24.
  • a further p-doped region 15 ' is arranged, which is separated from the p-doped region 15.
  • the further p-doped region 15 ' is connected via further contacts 19' to the second conductive layer 17 (not shown in FIG. 4).
  • FIG. 5 shows a variant of the arrangement of the transistor cells 2 of the second region 13.
  • the transistor cells 2 of the second region 13 are in this Embodiment arranged rectangular.
  • FIG. 6 shows a further variant of the arrangement of the transistor cells 2 of the first region 12 and of the transistor cells 2 of the second region 13.
  • the transistor cells 2 of the first region 12 and the transistor cells 2 of the second region 13 have a greater distance 30 from each other. While in the embodiments shown so far the distance between the transistor cells 2 of the first region 12 and the transistor cells 2 of the second region 13 only slightly exceeds the diameter of the transistor cells 2, the distance 30 according to FIG. 6 may correspond, for example, to ten times the diameter of the transistor cells 2 ,
  • FIG. 7 shows an embodiment in which the transistor cells 2 of the second region 13 are surrounded by a second cell region boundary 14 ', which in turn may be configured as a double trench structure.
  • the transistor cells 2 of the second region 13 are not embedded in the transistor cells 2 of the first region 12 or partially surrounded by them, but are arranged far away from the transistor cells 2 of the first region 12.
  • a corresponding opening of the thick oxide arranged in this area permits a connection to the sensor connection 18.
  • the transistor cells 2 of the second region 13 are surrounded by a further p-doped layer 15 '.
  • the transistor cells 2 of the first region 12 are surrounded by the p-doped layer 15 outside the first cell region boundary 14.
  • the p-doped layers 15 and 15 ' are separated from each other.
  • the p-doped layer 15 is connected to the first conductive layer 16 by means of the contacts 19 in analogy to the embodiments described above.
  • the further p-doped layer 15 ' is connected to the second conductive layer 17 via further contacts 19'.
  • the conductive layers 16 and 17 are in turn separated from each other. In this example, the doped layers 15 and 15 'are separated near the contacts 19'. But this gap could also be somewhere between 19 and 19 '. The same applies to the separation gap between the conductive layers 16 and 17.
  • the transistor cells 2 of the second region 13 are embedded together with the sensor connection 18 in the field of the transistor cells 2 of the first region 12.
  • the cell area boundary 14 is arranged so as to surround the sensor terminal 18.

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  • Semiconductor Integrated Circuits (AREA)

Abstract

La présente invention concerne un ensemble à semi-conducteurs d'un capteur de courant disposé dans un semi-conducteur de puissance comportant sur un substrat (1) un réseau de cellules de transistor (2) comprenant une électrode de grille dont les bornes d'émetteur (10) sont raccordées par l'intermédiaire d'une première couche conductrice (16) dans une première région (12) à au moins une borne de sortie (25) et dont les bornes d'émetteur (10) sont raccordées par l'intermédiaire d'une deuxième couche conductrice (17) dans une deuxième région (13) à au moins une borne de capteur (18) disposée à l'extérieur d'une première limite de zone de cellules (14) comprenant les cellules de transistor (2) de la première région (12) et les cellules du transistor (2) de la deuxième région (13), une structure de tranchée appartenant à la première limite de zone de cellules (14) étant formée entre les cellules de transistor (2) de la deuxième région (13) et de la borne de capteur (18), à laquelle est raccordée une couche dopée (15) reliée à la première couche conductrice (16) en direction du bord extérieur du substrat (1).
EP13702607.6A 2012-02-14 2013-01-25 Ensemble à semi-conducteurs d'un capteur de courant disposé dans un semi-conducteur de puissance Active EP2815430B8 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102012202180A DE102012202180A1 (de) 2012-02-14 2012-02-14 Halbleiteranordnung für einen Stromsensor in einem Leistungshalbleiter
PCT/EP2013/051415 WO2013120680A1 (fr) 2012-02-14 2013-01-25 Ensemble à semi-conducteurs d'un capteur de courant disposé dans un semi-conducteur de puissance

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EP2815430A1 true EP2815430A1 (fr) 2014-12-24
EP2815430B1 EP2815430B1 (fr) 2018-11-21
EP2815430B8 EP2815430B8 (fr) 2019-04-17

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US (1) US9478613B2 (fr)
EP (1) EP2815430B8 (fr)
JP (1) JP6095698B2 (fr)
CN (1) CN104106136B (fr)
DE (1) DE102012202180A1 (fr)
TW (1) TWI593083B (fr)
WO (1) WO2013120680A1 (fr)

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KR102153550B1 (ko) * 2019-05-08 2020-09-08 현대오트론 주식회사 전력 반도체 소자
KR20210065246A (ko) * 2019-11-26 2021-06-04 삼성디스플레이 주식회사 전자 장치
CN112968052B (zh) * 2020-12-23 2024-06-11 王培林 具有电流传感器的平面栅型功率器件及其制备方法

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US6180966B1 (en) * 1997-03-25 2001-01-30 Hitachi, Ltd. Trench gate type semiconductor device with current sensing cell
JP3450650B2 (ja) * 1997-06-24 2003-09-29 株式会社東芝 半導体装置
JP3413075B2 (ja) * 1997-09-16 2003-06-03 株式会社東芝 半導体装置およびその駆動方法
JP4829480B2 (ja) * 2004-05-10 2011-12-07 三菱電機株式会社 半導体装置
JP4807768B2 (ja) * 2004-06-23 2011-11-02 ルネサスエレクトロニクス株式会社 パワートランジスタ装置及びそれを用いたパワー制御システム
JP2007287988A (ja) * 2006-04-18 2007-11-01 Toyota Motor Corp 半導体装置
DE102006048910A1 (de) 2006-10-17 2008-04-24 Robert Bosch Gmbh Ausfallsicheres Parkassistenzsystem
JP2008235788A (ja) * 2007-03-23 2008-10-02 Sanyo Electric Co Ltd 絶縁ゲート型半導体装置
JP4577425B2 (ja) * 2007-11-07 2010-11-10 株式会社デンソー 半導体装置
US7939882B2 (en) * 2008-04-07 2011-05-10 Alpha And Omega Semiconductor Incorporated Integration of sense FET into discrete power MOSFET
FR2943341B1 (fr) 2009-03-19 2011-03-11 Sanofi Aventis Nouveaux derives d'indazole inhibiteurs d'hsp90,compositions les contenant et utilisation
JP5375270B2 (ja) 2009-03-31 2013-12-25 トヨタ自動車株式会社 半導体装置
KR101527270B1 (ko) * 2010-06-24 2015-06-09 미쓰비시덴키 가부시키가이샤 전력용 반도체 장치

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US20140374795A1 (en) 2014-12-25
JP6095698B2 (ja) 2017-03-15
US9478613B2 (en) 2016-10-25
WO2013120680A1 (fr) 2013-08-22
TWI593083B (zh) 2017-07-21
DE102012202180A1 (de) 2013-08-14
EP2815430B1 (fr) 2018-11-21
CN104106136B (zh) 2018-05-08
CN104106136A (zh) 2014-10-15
TW201347142A (zh) 2013-11-16
EP2815430B8 (fr) 2019-04-17
JP2015510697A (ja) 2015-04-09

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